lm5025bmtcx National Semiconductor Corporation, lm5025bmtcx Datasheet - Page 13

• Manufacturer Part Number: lm5025bmtcx
• Description: Active Clamp Voltage Mode Pwm Controller
• Manufacturer: National Semiconductor Corporation

Oscillator and Sync Capability
The LM5025B oscillator is set by a single external resistor
connected between the RT pin and GND. To set a desired
oscillator frequency (F), the necessary RT resistor can be
calculated from:
where F is in kHz and RT in kΩ.
The RT resistor should be located very close to the device
and connected directly to the pins of the IC (RT and GND).
A unique feature of LM5025B is the ability to synchronize the
oscillator to an external clock with a frequency that is either
higher or lower than the frequency of the internal oscillator.
The lower frequency sync frequency range is 80% of the free
running internal oscillator frequency. There is no constraint
on the maximum sync frequency. A minimum pulse width of
100ns is required for the synchronization clock . If the syn-
chronization feature is not required, the SYNC pin should be
connected to GND to prevent any abnormal interference .
The internal oscillator can be completely disabled by con-
necting the RT pin to REF. Once disabled, the sync signal
will act directly as the master clock for the controller. Both the
frequency and the maximum duty cycle of the PWM control-
ler can be controlled by the sync signal (within the limitations
of the Volt x Second Clamp). The maximum duty cycle (D)
will be (1-D) of the sync signal.
Feed-Forward Ramp
An external resistor (R
V
The slope of the signal at the RAMP pin will vary in propor-
tion to the input line voltage. This varying slope provides line
feedforward information necessary to improve line transient
response with voltage mode control. The RAMP signal is
compared to the error signal at the COMP pin by the pulse
width modulator comparator to control the duty cycle of the
main switch output. The Volt x Second Clamp comparator
also monitors the RAMP pin and if the ramp amplitude
exceeds 2.5V, the present cycle is terminated. The ramp
signal is reset to GND at the end of each cycle by either the
internal clock or the Volt x Second comparator, which ever
occurs first.
Soft-start
The soft-start feature allows the power converter to gradually
reach the initial steady state operating point, thus reducing
start-up stresses and surges. At power on, a 20µA current is
IN
and GND are required to create the PWM ramp signal.
RT = (4960/F)
FF
) and capacitor (C
1.02
FF
) connected to
13
sourced out of the soft-start pin (SS) into an external capaci-
tor. The capacitor voltage will ramp up slowly and will limit
the COMP pin voltage and therefore the PWM duty cycle. In
the event of a fault as determined by V
undervoltage (UVLO) or second level current limit, the output
gate drivers are disabled and the soft-start capacitor is fully
discharged. When the fault condition is no longer present a
soft-start sequence will be initiated. Following a second level
current limit detection (CS2), the soft-start current source is
reduced to 1µA until the first output pulse is generated by the
PWM comparator. The current source returns to the nominal
20µA level after the first output pulse ( ~ 1V at the SS pin).
The soft-start circuit controls the COMP pin voltage through
a unity gain amplifier with an open drain (sink only) output. If
the SS pin voltage is less than the PWM control signal
applied to the COMP pin, this amplifier will sink current from
the external pull-up connected to the COMP pin to force the
COMP voltage to follow the soft-start capacitor ramp. When
the soft-start capacitor charges to a voltage that is greater
than the control voltage applied to the COMP pin, the soft-
start amplifier automatically disengages, allowing closed
loop control of the PWM duty cycle. The soft-start amplifier
output stage is capable of sinking up to 5mA. External
pull-up circuits connected to the COMP pin must limit the
current into the pin to a value less than 5mA.
Thermal Protection
Internal Thermal Shutdown circuitry is provided to protect the
integrated circuit in the event the maximum junction tem-
perature is exceeded. When activated, typically at 165˚C,
the controller is forced into a low power standby state with
the output drivers and the bias regulator disabled. The de-
vice will restart after the thermal hysteresis (typically 25˚C).
During a restart after thermal shutdown, the soft-start ca-
pacitor will be fully discharged and then charged in the low
current mode (1µA) similar to a second level current limit
event. The thermal protection feature is provided to prevent
catastrophic failures from accidental device overheating.
CC
undervoltage, line
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