ncp5381 ON Semiconductor, ncp5381 Datasheet
ncp5381
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ncp5381 Summary of contents
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... NCP5381 2/3/4 Phase Buck Controller for VR10 and VR11 Pentium IV Processor Applications The NCP5381 is a two−, three−, or four−phase buck controller which combines differential voltage and current sensing, and adaptive voltage positioning to power Intel’s most demanding ® Pentium IV Processors and low voltage, high current power supplies. Dual− ...
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... NCP5381 PIN CONNECTIONS VID0 3 VID1 4 VID2 5 VID3 NCP5381 6 VID4 7 VID5 8 VID6 9 VID7 10 VR10/11 (Top View) http://onsemi.com DRVON 28 CS4 27 CS4N 26 CS3 25 CS3N 24 CS2 23 CS2N 22 CS1 21 CS1N ...
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... CS2 − CS2N Gain = 6 + CS3 − CS3N Gain = 6 + CS4 − CS4N Gain = 6 Oscillator ROSC ILIM EN VCC AGND 9.0 V Figure 1. Simplified Block Diagram NCP5381 NCP5381 + − + − Fault + − + − + − + − 4OFF OVER DIFFOUT 1.3 V Fault Logic + 3 Phase Detect − and Current Limit ...
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... DIFFOUT RFB 19 VFB RDRP 20 VDRP CD1 RD1 18 COMP CF RF ILIM 13 RLIM1 CH RLIM2 RT2 LOCATED NEAR OUTPUT INDUCTORS VCCP VSSP Figure 2. Application Schematic for Four Phases NCP5381 12 V_FILTER CVCC1 NCP3418B VCC RT1 3 OD VCC DGND RNTC2 14 2 AGND IN RNTC1 34 C1 VREF ...
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... DIFFOUT RFB 19 VFB RDRP 20 VDRP RD1 CD1 18 COMP RF ILIM RLIM1 RLIM2 RT2 LOCATED NEAR OUTPUT INDUCTORS VCCP VSSP Figure 3. Application Schematic for Three Phases NCP5381 12 V_FILTER CVCC1 NCP3418B VCC RT1 3 OD VCC DGND 14 RNTC2 2 AGND IN 34 RNTC1 VREF C1 38 ...
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... DIFFOUT RFB 19 VFB RDRP 20 VDRP CD1 RD1 18 COMP CF RF ILIM 13 RLIM1 CH RLIM2 RT2 LOCATED NEAR OUTPUT INDUCTORS VCCP VSSP Figure 4. Application Schematic for Two Phases NCP5381 12 V_FILTER CVCC1 NCP3418B VCC RT1 3 OD VCC DGND RNTC2 14 2 AGND IN RNTC1 34 C1 VREF ...
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... THPAD Copper pad on the bottom of the IC for heatsinking. This pin should be connected to the ground plane under the IC. NCP5381 Description pin. To guarantee correct operation, this pin should only be connected to the voltage OSC pin – do not connect this pin to any externally generated voltages. ...
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... Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: ESD Senstive Device. NCP5381 Rating ) on a thermally conductive PCB in free air θJA http://onsemi ...
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... Load = ±125 mA Maximum Output Voltage I SOURCE Minimum Output Voltage I SINK Output Source Current (Note 1) V Output Sink Current (Note Guaranteed by design. Not tested in production. NCP5381 = 0.1 mF, F < 13.2 V; All DAC Codes VCC Test Conditions Min −200 − −1 GND, − ...
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... Switching Frequency Accuracy R Switching Frequency Accuracy R R Output Voltage 10 kW < R OSC R Output Voltage (Note 1) 49.9 kW < R OSC 1. Guaranteed by design. Not tested in production. NCP5381 = 0.1 mF, F < 13.2 V; All DAC Codes VCC Test Conditions Min 5.7 = 25° 330 pF to GND, − GND L − ...
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... Output High Voltage Sinking 500 mA Output Low Voltage Rise Time C DVo = 10% to 90% Fall Time C DVo = 10% to 90% Internal Pulldown Resistance V 1. Guaranteed by design. Not tested in production. NCP5381 = 0.1 mF, F < 13.2 V; All DAC Codes VCC Test Conditions Min − − − − = 400 kHz − ...
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... External Pullup resistor of (Note 100 ms ≤ t VR_HOT Saturation Output Voltage I VR_HOT Output Leakage Current High Impedance State, VR_HOT = 5 Guaranteed by design. Not tested in production. NCP5381 = 0.1 mF, F < 13.2 V; All DAC Codes VCC Test Conditions Min = 10 mA − SINK − ...
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... Upper Threshold V Lower Threshold V Input Bias Current V Measured from the 1 st edge of Delay before Latching VID Change (VID De−Skewing) a VID change 1. Guaranteed by design. Not tested in production. NCP5381 = 0.1 mF, F < 13.2 V; All DAC Codes VCC Test Conditions Min < 1.1 V − SS PIN > ...
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... Negative Slew Rate Limit VID step range of −10mV to −500mV Voltage Reference (V ) REF V Output Voltage 0 < I REF Input Supply Current V Operating Current F CC NCP5381 = 0.1 mF, F < 13.2 V; All DAC Codes VCC Test Conditions Min 0.55 2.7 − − < 250 mA 3.92 VREF = 400 kHz − ...
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... NCP5381 = 0.1 mF, F < 13.2 V; All DAC Codes VCC Test Conditions Min − VID1 VID0 VID5 12 ...
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... NCP5381 VID1 VID0 VID5 12 ...
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... NCP5381 VID1 VID0 VID5 12 ...
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... NCP5381 = 0.1 mF, unless otherwise stated) < 13.2 V; All DAC Codes VCC Test Conditions VID4 VID3 VID2 VID1 12 ...
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... NCP5381 VID4 VID3 VID2 VID1 12 ...
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... NCP5381 VID4 VID3 VID2 VID1 12 ...
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... NCP5381 VID4 VID3 VID2 VID1 12 ...
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... Table 2: VR11 VID Codes VID7 VID6 VID5 800 mV 400 mV 200 mV 100 NCP5381 VID4 VID3 VID2 VID1 12 http://onsemi.com 22 VID0 Nominal 6.25 mV DAC ...
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... T , AMBIENT TEMPERATURE (°C) A Figure 7. ROSC Voltage vs. Ambient Temperature 15.0 14.8 14.6 14.4 14.2 14 AMBIENT TEMPERATURE (°C) A Figure 9. IC Quiescent Current vs. Ambient Temperature NCP5381 TYPICAL CHARACTERISTICS 250 240 230 220 210 200 Figure 6. VR Ready Delay Time vs. Ambient 5.20 5.10 5.00 4.90 4. ...
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... Figure 13. VR_HOT Threshold Voltage vs. Ambient Temperature 1.0 0.9 Enable Increasing Voltage 0.8 Enable Decreasing Voltage 0.7 0.6 0 AMBIENT TEMPERATURE (°C) A Figure 15. Enable Threshold Voltage vs. Ambient Temperature NCP5381 TYPICAL CHARACTERISTICS 1.5 1.4 1.3 1.2 1 Figure 12. VR_FAN Turn On & Turn Off Threshold Voltage vs. Ambient Temperature ...
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... Lockout, Soft−Start, Overcurrent Protection, Overvoltage Protection, and Power Good Monitor. Remote Output Sensing Amplifier (RSA) A true differential amplifier allows the NCP5381 to measure Vcore voltage feedback with respect to the Vcore ground reference point by connecting the Vcore reference point to VS+, and the Vcore ground reference point to VS−. ...
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... VR_RDY pin will be set low until the output rises. Soft−Start The NCP5381 incorporates an externally programmable soft−start. The soft−start circuit works by controlling the ramp−up of the DAC voltage during powerup. The initial soft−start pin voltage The soft−start circuitry clamps ...
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... NCP5381 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 Boot 0.8 Dwell Time 0.6 0.4 0.2 0 TIME 0 Figure 18. Typical VR11 Soft−Start Sequence to Vcore = 1.3 V http://onsemi.com 27 VID Setting Boot Voltage NCP5381 Internal Dynamic VID Rate Limit Vcore Voltage SS Pin Voltage ...
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... The NCP5381 is a high performance multiphase controller optimized to meet the Intel VR11 Specifications. The demo board for the NCP5381 is available by request configured as a four phase solution with decoupling designed to provide a 1.0 mW load line under a 100 A step load. A schematic is available upon request from ON Semiconductor ...
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... VID selection, then enable the test. See Figures 21 through 23. Figure 21. 1.6 to 0.5 Dynamic VID Response Figure 22. Dynamic VID Settling Time Rising Figure 23. Dynamic VID Settling Time Falling NCP5381 Design Methodology Decoupling the V Pin on the input filter is required as shown in the V minimize supply noise on the IC ...
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... A at 100°C. The total sensed current can be observed as a scaled voltage at the VDRP pin added to a positive, no−load offset of approximately 1.3 V. NCP5381 resistance and frequency is inversely proportional to the resistance. The resistance may be estimated by equation 2. This equation is valid for the individual phase frequency in both three and four phase mode ...
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... Inductor Current Sense Compensation The NCP5381 uses the inductor current sensing method. This method uses an RC filter to cancel out the inductance of the inductor and recover the voltage that is the result of Rsense(T) + Figure 27. The demoboard inductor measured 350 nH and 0. room temp. The actual value used for Rsense was 953 W which matches the equation for Rsense at approximately 50C ...
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... DC−DC converter must have sufficiently high gain to control the output impedance completely. Standard Type−3 compensation works well with the NCP5381. RFB1 should be kept above 50 W for amplifier stability reasons. The goal is to compensate the system such that the ...
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... NTC. The actual selection of the NTC will be effected by the location of the output inductor with respect to the NTC and airflow, and should be verified with an actual system thermal solution. NCP5381 RRDP determines the target output impedance by the basic equation: Vout RDRP + RFB · ...
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... Allegro Free Physical Viewer 15.x from the Cadence website http://www.cadence.com/. NCP5381 further details. The OVP circuit monitors the output of DIFFOUT. If the DIFFOUT signal reaches 180 mV above the nominal 1.3 V offset the OVP will trip. The DIFFOUT signal is the difference between the output voltage and the DAC voltage plus the 1 ...
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... COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF b 0.18 0.30 D 7.00 BSC D2 5.50 5.70 E 7.00 BSC E2 5.50 5.70 e 0.50 BSC L 0.30 0.50 k 0.20 −−− ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCP5381/D ...