lm2633mtd National Semiconductor Corporation, lm2633mtd Datasheet - Page 33

• Manufacturer Part Number: lm2633mtd
• Description: Advanced Two-phase Synchronous Triple Regulator Controller For Notebook Cpus
• Manufacturer: National Semiconductor Corporation

Control Loop Design
The signal path from output voltage to control voltage is the
feedback path. It typically contains a voltage divider, an error
amplifier and a compensation network. Those are shown In
Figure 7 as R
of the LM2633, since an R-2R ladder network is used, R
and R
regarding their values and ratios, refer to Table 5 . For Chan-
nel 2, R
resistors.
VID4:0
00000
00001
00010
00011
00100
00101
00110
01000
01001
01010
01011
01100
01101
10000
10001
10010
10011
10100
10101
10110
11000
11001
11010
00111
01110
01111
10111
11011
11100
11101
11110
11111
2
values change with the VID setting. For information
1
TABLE 5. R1 and R2 Values vs. VID
and R
1
V
NO CPU
, R
1. 075
DAC
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.050
1.025
1.000
0.975
0.925
0.900
2.00
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
0.95
2
2
, the gm amplifier, and Z
are simply the external voltage divider
(V)
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
12.5k
25k
25k
25k
25k
25k
25k
25k
25k
25k
25k
25k
25k
25k
25k
25k
25k
R
1
(Continued)
17.1k
18.4k
17.4k
21.4k
19.3k
22.0k
22.1k
30.0k
24.5k
27.3k
26.0k
34.6k
29.3k
36.0k
36.4k
64.3k
23.2k
25.7k
24.5k
32.1k
27.5k
33.3k
33.6k
56.2k
39.6k
47.4k
43.4k
75.0k
53.7k
81.8k
83.7k
R
2
c
. For Channel 1
R2/(R1+R2)
0.41
0.42
0.41
0.46
0.43
0.47
0.47
0.55
0.49
0.52
0.51
0.58
0.54
0.59
0.59
0.72
0.65
0.67
0.66
0.72
0.69
0.73
0.73
0.82
0.76
0.79
0.78
0.86
0.81
0.87
0.87
r =
1
1
33
To achieve the gain shape in Figure 10 , Z
take the form of two RC branches in parallel, as shown in
Figure 11 . In the scheme, C1 and R3 form the first zero f
C2 and R3 form the second pole f
second zero f
The gain of the compensation network can be calculated as
the following. If the ESR zero frequency f
low frequency pole f
section from f
such as shown in Figure 9 . Find the frequency where this
section (or the extension of this section) crosses 0dB by
using the following equation:
If the desired loop transfer function cross-over frequency is
f
be:
To determine the component values in Figure 11 , the follow-
ing equations can be used:
where B is the desired gain at f
ductance of the error amplifier.
FIGURE 10. 2-Pole 2-Zero (lag-lag) Network Asymptotic
c_c
, then the gain of the compensation network at f
FIGURE 11. Compensation Network
p
z2
(310 Hz) to f
.
p
, then there should be a −20dB/decade
f
c_o
Gain Plot
z
= M • f
(8.8 kHz) in the plant gain plot,
z1
p2
, and g
p
, and C2 and R4 form the
c
z
m
in Figure 7 should
is higher than the
is the transcon-
www.national.com
20000865
20000864
p
should
(41)
(42)
(43)
(44)
z1
,