lm2618 National Semiconductor Corporation, lm2618 Datasheet - Page 11

• Manufacturer Part Number: lm2618
• Description: 400ma Sub-miniature, High Efficiency, Synchronous Pwm & Pfm Programmable Dc-dc Converter
• Manufacturer: National Semiconductor Corporation

PFM Operation
Connecting the SYNC/MODE pin to SGND sets the LM2618
to hysteretic PFM operation. While in PFM (Pulse Frequency
Modulation) mode, the output voltage is regulated by switch-
ing with a discrete energy per cycle and then modulating the
cycle rate, or frequency, to control power to the load. This is
done by using an error comparator to sense the output
voltage and control the PFET switch. The device waits as the
load discharges the output filter capacitor, until the output
voltage drops below the lower threshold of the PFM error-
comparator. Then the error comparator initiates a cycle by
turning on the PFET switch. This allows current to flow from
the input, through the inductor to the output, charging the
output filter capacitor. The PFET switch is turned off when
the output voltage rises above the regulation threshold of the
PFM error comparator. After the PFET switch turns off, the
output voltage rises a little higher as the inductor transfers
stored energy to the output capacitor by pushing current into
the output capacitor. Thus, the output voltage ripple in PFM
mode is proportional to the hysteresis of the error compara-
tor and the inductor current.
In PFM mode, the device only switches as needed to service
the load. This lowers current consumption by reducing power
consumed during the switching action in the circuit due to
transition losses in the internal MOSFETs, gate drive cur-
rents, eddy current losses in the inductor, etc. It also im-
proves light-load voltage regulation. During the second part
of the cycle, the NFET synchronous rectifier turns on until
the error comparator initiates the next cycle or the inductor
current ramps near zero. A zero crossing detector turns off
the NFET synchronous rectifier if the inductor current ramps
near zero.
Operating Mode Selection
(SYNC/MODE Pin)
The SYNC/MODE digital input pin is used to select between
PWM or PFM operating modes. Set SYNC/MODE high
(above 1.3V) for 600kHz PWM operation when the system is
active and the load is above 50mA. Set SYNC/MODE low
(below 0.4V) to select PFM mode when the load is less than
50mA for precise regulation and reduced current consump-
tion when the system is in standby. The LM2618 has an
over-voltage protection feature that activates if the device is
left in PWM mode under low-load conditions (
prevent the output voltage from rising too high. See Over-
voltage Protection, for more information.
Select modes with the SYNC/MODE pin using a signal with
a slew rate faster than 5V/100µs. Use a comparator Schmitt
trigger or logic gate to drive the SYNC/MODE pin. Do not
leave the pin floating or allow it to linger between logic levels.
These measures will prevent output voltage errors that could
otherwise occur in response to an indeterminate logic state.
Ensure a minimum load to keep the output voltage in regu-
lation when switching modes frequently. The minimum load
requirement varies depending on the mode change fre-
quency. A typical load of 8µA is required when modes are
changed at 100 ms intervals, 85µA for 10 ms and 800µA for
1 ms.
Frequency Synchronization
(SYNC/MODE Pin)
The SYNC/MODE input can also be used for frequency
synchronization. To synchronize the LM2618 to an external
clock, supply a digital signal to the SYNC/MODE pin with a
<
50mA) to
11
voltage swing exceeding 0.4V to 1.3V. During synchroniza-
tion, the LM2618 initiates cycles on the rising edge of the
clock. When synchronized to an external clock, it operates in
PWM mode. The device can synchronize to an external
clock over frequencies from 500kHz to 1MHz.
Use the following waveform and duty-cycle guidelines when
applying an external clock to the SYNC/MODE pin. Each
clock cycle should have high and low periods between 1.3µs
and 200ns and a duty cycle between 30% and 70%. The
total clock period should be 2µs or less. Clock under/
overshoot should be less than 100mV below GND or above
VDD. When applying noisy clock signals, especially sharp
edged signals from a long cable during evaluation, terminate
the cable at its characteristic impedance; add an RC filter to
the SYNC pin, if necessary, to soften the slew rate and
over/undershoot. Note that sharp edged signals from a pulse
or function generator can develop under/overshoot as high
as 10V at the end of an improperly terminated cable.
Overvoltage Protection
The LM2618 has an over-voltage comparator that prevents
the output voltage from rising too high when the device is left
in PWM mode under low-load conditions. Otherwise, the
output voltage could rise out of regulation from the minimum
energy transferred per cycle due to the 200ns minimum
on-time of the PFET switch while in PWM mode. When the
output voltage rises by 50mV over its regulation threshold,
the OVP comparator inhibits PWM operation to skip pulses
until the output voltage returns to the regulation threshold. In
over voltage protection, output voltage and ripple increase
slightly.
Shutdown Mode
Setting the EN input pin to SGND places the LM2618 in a
0.02µA (typ) shutdown mode. During shutdown, the PFET
switch, NFET synchronous rectifier, reference, control and
bias of the LM2618 are turned off. Setting EN high to VDD
enables normal operation. While turning on, soft start is
activated.
EN must be set low to turn off the LM2618 during undervolt-
age conditions when the supply is less than the 2.8V mini-
mum operating voltage. The LM2618 is designed for mobile
phones and similar applications where power sequencing is
determined by the system controller and internal UVLO (Un-
der Voltage LockOut) circuitry is unnecessary. The LM2618
has no UVLO circuitry. Although the LM2618 exhibits safe
behavior while enabled at low input voltages, this is not
guaranteed.
Internal Synchronous Rectification
The LM2618 uses an internal NFET as a synchronous rec-
tifier to improve efficiency by reducing rectifier forward volt-
age drop and associated power loss. In general, synchro-
nous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low com-
pared to the voltage drop across an ordinary rectifier diode.
Under moderate and heavy loads, the internal NFET syn-
chronous rectifier is turned on during the inductor current
down-slope in the second part of each cycle. The synchro-
nous rectifier is turned off prior to the next cycle, or when the
inductor current ramps near zero at light loads. The NFET is
designed to conduct through its intrinsic body diode during
transient intervals before it turns on, eliminating the need for
an external diode.
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