ice3ar4780jz Infineon Technologies Corporation, ice3ar4780jz Datasheet - Page 13

• Manufacturer Part Number: ice3ar4780jz
• Description: Off-line Smps Current Mode Controller With Integrated 800v Coolmos And Startup Cell Brownout & Frequency Jitter In Dip- 7
• Manufacturer: Infineon Technologies Corporation

Version 2.0
to low in order to disable power transfer to the secondary
side.
3.6
Figure 17
There is a cycle by cycle peak current limiting operation
realized by the Current-Limit comparator C10. The source
current of the integrated CoolMOS
sense resistor R
transformed to a sense voltage V
CS. If the voltage V
voltage V
gate drive by resetting the PWM Latch FF1.
A Propagation Delay Compensation is added to support the
immediate shut down of the integrated CoolMOS
short propagation delay. Thus the influence of the AC input
voltage on the maximum output power can be reduced to
minimal. This compensation applies to both the peak load
and burst mode.
In order to prevent the current limit from distortions caused
by leading edge spikes, a Leading Edge Blanking (LEB) is
integrated in the current sense path for the comparators C10,
C12 and the PWM-OP.
The output of comparator C12 is activated by the Gate G10
if Active Burst Mode is entered. When it is activated, the
current limiting is reduced to V
determines the maximum power level in Active Burst Mode.
PWM Latch
FBB
V
Active Burst
FB_burst
FF1
Mode
PWM-OP
G10
&
csth,
Current Limiting
C5
the comparator C10 immediately turns off the
Propagation-Delay
Current Limiting Block
Sense
Compensation
. By means of R
Compensation-Burst
Propagation-Delay
C10
Sense
G13
or
C12
exceeds the internal threshold
Sense
csth_burst
V
CS
csth
®
Sense
is sensed via an external
which is fed into the pin
Current Limiting
V
CSth_burst
220ns
180ns
the source current is
. This voltage level
LEB
LEB
10k
D1
®
with very
1pF
S4
13
3.6.1
Figure 18
Whenever the integrated CoolMOS
leading edge spike is generated due to the primary-side
capacitances and reverse recovery time of the secondary-side
rectifier. This spike can cause the gate drive to switch off
unintentionally. In order to avoid a premature termination of
the switching pulse, this spike is blanked out with a time
constant of t
burst mode.
3.6.2
In case of overcurrent detection, there is always propagation
delay to switch off the integrated CoolMOS
of the peak current I
depends on the ratio of dI/dt of the peak current (Figure 19).
Figure 19
The overshoot of Signal2 is larger than of Signal1 due to the
steeper rising waveform. This change in the slope is
depending on the AC input voltage. Propagation Delay
Compensation is integrated to reduce the overshoot due to
dI/dt of the rising primary current. Thus the propagation
delay time between exceeding the current sense threshold
V
compensated over temperature within a wide input range.
Current Limiting is then very accurate.
I
I
I
csth
V
peak2
peak1
Limit
csth
and the switching off of the integrated CoolMOS
V
I
Sense
Sense
LEB
Propagation Delay Compensation
(patented)
Leading Edge Blanking
Leading Edge Blanking
Current Limiting
= 220ns for normal load and t
I
Overshoot2
Signal2
peak
t
LEB
is induced to the delay, which
Functional Description
= 220ns/180ns
CoolSET
ICE3AR4780JZ
Signal1
®
t
is switched on, a
Propagation Delay
®
26 Aug 2010
LEB
. An overshoot
®
I
Overshoot1
-F3R80
= 180ns for
t
t
®
is