ncp1082 ON Semiconductor, ncp1082 Datasheet - Page 14

• Manufacturer Part Number: ncp1082
• Description: Integrated Poe-pd & Dc-dc Converter Controller With 9v Auxiliary Supply Support
• Manufacturer: ON Semiconductor

voltage to a 9 V output on the VDDH pin. VDDH supplies
the internal gate driver circuit which drives the GATE pin
and the gate of the external power MOSFET. The NCP1082
gate driver supports an external MOSFET with high Vth and
high input gate capacitance. A second LDO regulator steps
down the VDDH voltage to a 3.3 V output on VDDL. VDDL
powers the analog circuitry of the DC−DC controller.
include power−on−reset (POR) detectors which prevent the
DC−DC controller from operating when either VDDH or
VDDL is too low. In addition, an over−voltage lockout
(OVLO) on the VDDH supply disables the gate driver in case
of an open−loop converter with a configuration using the bias
winding of the transformer (see Figure 4).
VPORT reaches the Vuvlo_on threshold.
internal error amplifier of the NCP1082 and the internal
1.2 V reference voltage regulate the DC−DC output voltage.
In this configuration, the feedback loop compensation
network should be inserted between the FB and COMP pins
as shown in Figures 3, 4 and 5.
DC−DC Converter Controller
Internal VDDH and VDDL Regulators and Gate Driver
Error Amplifier
The NCP1082 implements a current mode DC−DC converter controller which is illustrated in Figure 14.
An internal linear regulator steps down the VPORTP
In order to prevent uncontrolled operations, both regulators
Both VDDH and VDDL regulators turn on as soon as
In non−isolated converter topologies, the high gain
COMP
CS
SS
FB
Blanking
1.2 V
time
Current Slope
Compensation
VDDL
5 mA
11 kW
Soft−start
VDDL
Figure 14. DC−DC Controller Block Diagram
5 kW
10 mA
0
2
1.45 V
360 mV
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Current limit
PWM comp
comp
14
Reset
because it is already implemented externally with the shunt
regulator on the secondary side of the DC−DC controller
(see Figure 2). Therefore the FB pin must be strapped to
ARTN and the output transistor of the opto−coupler has to
be connected on the COMP pin where an internal 5 kW
pull−up resistor is tied to the VDDL supply (see Figure 14).
the output voltage to ramp up in a controlled fashion,
eliminating output voltage overshoot. This function is
programmed by connecting a capacitor Css between the SS
and ARTN pins.
is fully discharged. After coming out of POR, an internal
current source of 5 mA typically starts charging the capacitor
Css to initiate soft−start. When the voltage on SS pin has
reached 0.45 V (typical), the gate driver is enabled and
DC−DC operation starts with a duty cycle limit which
increases with the SS pin voltage. The soft−start function is
finished when the SS pin voltage goes above 1.6 V for which
the duty cycle limit reaches its maximum value of 80
percent.
equation:
CLK
Soft−Start
Generator
Oscillator
Sawtooth
In isolated topologies the error amplifier is not used
The soft−start function provided by the NCP1082 allows
While the DC−DC controller is in POR, the capacitor Css
Soft−start can be programmed by using the following
OSC
&
CLK
Set
tss(ms) + 0.23
S
R
Q
VPORTP
Gate
Driver
3.3 V LDO
9 V LDO
Css(nf)
VDDL
VDDH
GATE
ARTN