74VHCT374AN Fairchild Semiconductor, 74VHCT374AN Datasheet
74VHCT374AN
Specifications of 74VHCT374AN
Related parts for 74VHCT374AN
74VHCT374AN Summary of contents
Page 1
... MTC20 Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B. Connection Diagram ©1997 Fairchild Semiconductor Corporation 74VHCT374A Rev. 1.3 General Description 25°C The VHCT374A is an advanced high speed CMOS octal ...
Page 2
... LOW-to-HIGH Transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1997 Fairchild Semiconductor Corporation 74VHCT374A Rev. 1.3 Functional Description The VHCT374A consists of eight edge-triggered flip- flops with individual D-type inputs and 3-STATE true out- puts ...
Page 3
... OUT 3. When outputs are in OFF-State or when GND (Outputs Active). OUT OUT CC 5. Unused inputs must be held HIGH or LOW. They may not float. ©1997 Fairchild Semiconductor Corporation 74VHCT374A Rev. 1.3 Parameter (4) (5) Parameter 5.0V ± 0. Rating – ...
Page 4
... OLV Dynamic V OL (6) V Minimum HIGH Level Dynamic IHD Input Voltage (6) V Maximum LOW Level Dynamic ILD Input Voltage Note: 6. Parameter guaranteed by design. ©1997 Fairchild Semiconductor Corporation 74VHCT374A Rev. 1.3 V (V) Conditions Min. Typ. Max. Min. Max. CC 4.5 5.5 4.5 5.5 4 – ...
Page 5
... V • can be calculated by the equation Operating Requirements Symbol Parameter t (H), t (L) Minimum Pulse Width (CP Minimum Set-up Time S t Minimum Hold Time H ©1997 Fairchild Semiconductor Corporation 74VHCT374A Rev. 1.3 V (V) Conditions CC 5.0 ± 0.5 C 15pF L C 50pF L 5.0 ± 0 15pF 50pF L 5.0 ± ...
Page 6
... Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide ©1997 Fairchild Semiconductor Corporation 74VHCT374A Rev. 1.3 Package Number M20B 6 www.fairchildsemi.com ...
Page 7
... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide ©1997 Fairchild Semiconductor Corporation 74VHCT374A Rev. 1.3 Package Number M20D 7 www.fairchildsemi.com ...
Page 8
... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide ©1997 Fairchild Semiconductor Corporation 74VHCT374A Rev. 1.3 Package Number MTC20 8 www.fairchildsemi.com ...
Page 9
... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ® ACEx Across the board. Around the world.™ ActiveArray™ Bottomless™ Build it Now™ CoolFET™ CorePLUS™ ...