at17lv002a-10q1 ATMEL Corporation, at17lv002a-10q1 Datasheet - Page 4

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at17lv002a-10q1

Manufacturer Part Number
at17lv002a-10q1
Description
Fpga Configuration Eeprom Memory
Manufacturer
ATMEL Corporation
Datasheet
Figure 1. Configuration with a Single AT17A Series Configurator
Notes:
Figure 2. Configuration with Multiple AT17A Series Configurators
Notes:
4
0.1
0.1
V
CC
m
m
GND
F
F
GND
1 k
1 k
1. Use of the READY pin is optional.
2. Introducing an RC delay to the input of nCONFIG is recommended to ensure that V
3. Reset polarity of EEPROM must be set active Low (OE active High).
1. Use of the READY pin is optional.
2. Introducing an RC delay to the input of nCONFIG is recommended to ensure that V
3. Reset polarity of EEPROM must be set active Low (OE active High).
W
AT17C/LV002A
W
configuration begins. (nCONFIG can instead be connected to an active Low system reset signal.)
configuration begins. (nCONFIG can instead be connected to an active Low system reset signal.)
nCONFIG
MSEL1
MSEL0
nCE
nCONFIG
nCE
MSEL0
MSEL1
EPF6K/EPF10K
EPF10K
CONF_DONE
CONF_DONE
nSTATUS
DCLK
nSTATUS
DATA0
DCLK
V
CC
1 k
W
V
CC
1 k
V
W
CC
1 k
AT17LV512A/010A/020A/002A
AT17C512A/010A/020A/002A
W
DCLK
DATA
nCS
OE
(1)(2)(3)
(1)(2)(3)
DEVICE 1
V
READY
nCASC
CC
1 k
W
AT17LV512A/010A/020A/002A
AT17C512A/010A/020A/002A
AT17LV512A/010A/020A/002A
AT17C512A/010A/020A/002A
DCLK
DATA
DCLK
DATA
nCS
OE
nCS
OE
CC
CC
DEVICE 2
(5V/3.3V) is reached before
(5V/3.3V) is reached before
SER_EN
SER_EN
READY
2280B–08/01
V
V
CC
CC

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