th58nvg1s3aft05 TOSHIBA Semiconductor CORPORATION, th58nvg1s3aft05 Datasheet
th58nvg1s3aft05
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th58nvg1s3aft05 Summary of contents
Page 1
... ALE Address latch enable Write protect Ready / Busy I/O4 I/O3 GND Ground Input I/O2 I/O1 V Power supply Ground TH58NVG1S3AFT05 1E5 Cycles(With ECC) 25 Psmax 50 ns min 10 mA typ typ typ max 000707EBA1 2003-05-19A 1/32 ...
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... Control circuit HV generator VALUE 0.6 to 4.6 0.6 to 4 ½ 0.3 260 -55 to 150 CONDITION MIN OUT TH58NVG1S3AFT05 Column buffer Column decoder Data register Sense amp Memory cell array UNIT °C °C °C MAX UNIT 20 pF ...
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... OUT mA OUT cycle 0V/VCC 0 0V/VCC CC , Vcc 400 Vcc pin V 0 TH58NVG1S3AFT05 TYP. MAX UNIT - 2048 Blocks TYP. MAX UNIT 3 0.8 V MIN TYP. MAX UNIT ...
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... CLSTO t RE High to WE Low RHW t WE High to CE Low WHC t WE High to RE Low WHR t Memory Cell Array to Starting Address High to Busy WB t Device Reset Time (Read/Program/Erase) RST PARAMETER TH58NVG1S3AFT05 MIN MAX UNIT NOTES ...
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... CC SYMBOL PARAMETER t Average Programming Time PROG Number of Programming Cycles on Same Page N (per 512+16 bytes) t Block Erasing Time BERASE (1) Refer to Application Note (12) toward the end of this document. TH58NVG1S3AFT05 CONDITION 2.4 V, 0.4 V 3ns 1.5 V, 1.5 V 1 (100 pF TTL L MIN TYP. MAX UNIT NOTES ...
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... TIMING DIAGRAMS Latch Timing Diagram for Command/Address /Data CLE ALE I/O Command Input Cycle Timing Diagram CLE t CLS ALS ALE t DS I/O Setup Time Hold Time CLH ALH t DH TH58NVG1S3AFT05 : 2003-05-19A 6/32 ...
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... CA8 to11 PA0 TH58NVG1S3AFT05 ALH PA8 to 15 PA16 : CLH ...
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... REH RHZ REA RHZ t CLSTO t CLH WHC CSTO t WHR TH58NVG1S3AFT05 t CEA CHZ REA RHZ t CHZ RSTO t RHZ Status output : 2003-05-19A 8/32 ...
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... PA0 to 7 PA8 to 15 PA16 CA8 CLS ALH ALS PA0 to 7 PA8 to 15 PA16 TH58NVG1S3AFT05 t CLEA t CLS CLH CEA REA D OUT 30H N Data out from Col ...
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... ALS t ALH PA0 to PA8 to 30H PA16 Page address P TH58NVG1S3AFT05 t CLEA CLH CEA REA OUT OUT Page address P Column address A 1 Continues next page ...
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... CLH ALS ALH ALS CA0 to CA8 to E0H 7 11 Column address B Column address TH58NVG1S3AFT05 t CLEA CEA REA D D OUT OUT OUT N’ Page address P B 2003-05-19A 11/32 ...
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... I/O CA0 to CA8 to PA0 to 80H ALH t ALS PA8 PA16 not input data while data is being output TH58NVG1S3AFT05 t Prog Status 10H 70H output D 2111* IN 2003-05-19A 12/32 ...
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... ALE I/O PA8 to PA0 to 60H 15 7 Auto Block Erase Setup command : ALH BERASE PA16 D0H Busy Erase Start command : Do not input data while data is being output. TH58NVG1S3AFT05 Status 70H output Status Read command 2003-05-19A 13/32 ...
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... ALS t ALEA ALE RE tDH tDH t REAID 90H 00H I/O ID Read Address command 00 t CEA REAID REAID REAID 98H DAH Note1 Maker code Device code Note1 : 81H or 01H Note2 : 95H or 15H Note3 : 44H or C4H TH58NVG1S3AFT05 t REAID Note2 Note3 : 2003-05-19A 14/32 ...
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... Busy state ( during the Program, Erase and Read operations and will return to Ready state ( after completion of the operation. The output buffer for this signal is an open drain and has to be pulled-up to Vccq with appropriate resister.. TH58NVG1S3AFT05 ...
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... PA9 PA8 PA16 CLE ALE TH58NVG1S3AFT05 CA0 to CA11 : Column address PA0 to PA16 : Page address PA6 to PA16 : Block address PA0 to PA5 : NAND address in block * V/Vcc * * 2003-05-19A 16/32 ...
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... First Cycle Second Cycle I/ TH58NVG1S3AFT05 Acceptable while Busy Ó Ó I/O1 to I/O8 Power Data output Active High impedance Active High impedance Standby High Impedance Active 2003-05-19A 17/32 ...
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... In the serial data out from the register, the column address can be changed by inputting the column address with 05h and E0h commands. The data are read out in serial from the column address which Cell array is input to the device by 05h and E0h commands with /RE clock. TH58NVG1S3AFT05 M+1 M+2 M Page Address N E0H M’ ...
Page 19
... If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. after the Erase Start command “DOH” Status Read command Busy TH58NVG1S3AFT05 Status 70h Out Pass I/O Fail 2003-05-19A 19/32 ...
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... Descripton I/O8 I/O7 I/ level cell 4 level cell 8 level cell 16 level cell TH58NVG1S3AFT05 Note2 Note3 Note1 : 81H or 01H Note2 : 95H or 15H Note3 : 44H or C4H I/O2 I/O1 Hex Data 98H DAH 81H or 01H ...
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... Reserved Reserved X8 0 X16 Descripton I/O8 I/O7 I/ 64Mb 0 0 128Mb 0 0 256Mb 0 1 512Mb 0 1 1Gb 1 0 2Gb 1 0 4Gb 1 1 8Gb TH58NVG1S3AFT05 I/O5 I/O4 I/O3 I/O2 I/ I/O5 I/O4 I/O3 I/O2 I/ ...
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... Ready state. Busy: 0 Busy: 0 Not Protected Device 2 3 Busy 70H Status on Device N pin signals from multiple devices are wired together as shown in the TH58NVG1S3AFT05 The Pass/Fail status on I/O1 and I/ Device Device 2003-05-19A 22/32 ...
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... BY The second FF t (max RST Figure (max 500 P s) RST Figure 9. FF Figure 10. t (max RST 70 ( command is invalid, but the third FF Figure 12. TH58NVG1S3AFT05 I/O status : Pass/Fail o Pass : Ready/Busy o Ready (2) ( command is valid. 2003-05-19A 23/32 ...
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... Stored data may be corrupted if an unknown command is entered during the command cycle. (4) Restriction of command while Busy state During Busy state, do not input any command except 70H, and FFH 1ms max Operation Figure 15. Power-on/off Sequence FF Reset Figure 16. TH58NVG1S3AFT05 don’t care V IL don’t care 2003-05-19A 24/32 ...
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... Page 0 (1) Page 1 (2) Page 2 (3) Page 31 (32) Page 63 (64 Mode specified by the command. Ex.) Random page program (Prohibition) DATA IN: Data (1) Page 0 Page 1 Page 2 Page 31 Page 63 Figure 17. page programming within a block TH58NVG1S3AFT05 Programming cannot be executed. Data (64) Data register (2) (32) (3) (1) (64) 2003-05-19A 25/32 ...
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... Ready 1.0 V Busy Figure 20. TH58NVG1S3AFT05 00 [A] Status output Status Read 80 10 Address Data N input / BY buffer consists of an open drain 3 25° 100 ...
Page 27
... The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN (100 ns MIN) WW Disable Programming WE DIN (100 ns MIN) WW Enable Erasing WE 60 DIN (100 ns MIN) WW Disable Erasing WE DIN (100 ns MIN) WW TH58NVG1S3AFT05 2003-05-19A 27/32 ...
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... When six address cycles are input Although the device may read in sixth address ignored inside the chip. Read operation CLE CE WE ALE I/O 00H Program operation CLE CE WE ALE 80H I/O Address input ignored Address input Figure 22. ignored Figure 23. TH58NVG1S3AFT05 30H Data input 2003-05-19A 28/32 ...
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... Note: The input data for unprogrammed or previously programmed page segments must be "1" (i.e. the inputs for all page bytes outside the segment which programmed should be set to all “1”). : 512 bytes x 4 segments All 1s Data Pattern 2 All 1s All 1s Data Pattern 2 Figure 24. TH58NVG1S3AFT05 Data Pattern 8 Data Pattern 8 2003-05-19A 29/32 ...
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... Bad Block *1 Block No. 2048 Yes End ç ç ç ç ç ç ç Figure 27. TH58NVG1S3AFT05 TYP. MAX UNIT - 2048 Block of each block. If the column address 0 or 2048 of the 1st page or the 2nd page is not FF (Hex), define the block as a bad block. ...
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... DETECTION AND COUNTERMEASURE SEQUENIE When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an external buffer. Then, Block A prevent further system accesses to Block creating a bad block table or by using another appropriate scheme). Block B Figure 28. TH58NVG1S3AFT05 2003-05-19A 31/32 ...
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... Package Dimensions Weight: 0.53 g (typ.) TH58NVG1S3AFT05 2003-05-19A 32/32 ...