e28f016xd Intel Corporation, e28f016xd Datasheet - Page 32

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e28f016xd

Manufacturer Part Number
e28f016xd
Description
16-mbit 1 Mbit X 16 Dram-interface Flash Memory
Manufacturer
Intel Corporation
Datasheet

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28F016XD FLASH MEMORY
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Sampled, but not 100% tested. Guaranteed by design.
11. See AC Input/Output Reference Waveforms for timing measurements.
32
Operation within the t
Assumes that t
t
t
t
characteristics only. If t
the duration of the cycle. If t
data output will contain the data read from the selected address. If neither of the above conditions are satisfied, the
condition of the data out is indeterminate.
Either t
These parameters are referenced to the CAS# leading edge in early write cycles and to the WE# leading edge in read-
write cycles.
Operation within the t
is greater than the specified t
Refer to command definition tables for valid address and data values.
AR
OFF(max)
WCS
, t
, t
WCR
RWD
RCH
defines the time at which the output achieves the open circuit condition and is not referenced to V
, t
, t
DHR
or t
CWD
are referenced to t
RRH
RCD
and t
must be satisfied for a read cycle.
t
RCD(max)
RCD(max)
RAD(max)
AWD
WCS
are non restrictive operating parameters. They are included in the datasheet as electrical
CWD
RAD(max)
.
t
limit insures that t
limit ensures that t
WCS(min)
RAD(max)
t
CWD(min)
limit, then the access time is controlled by t
the cycle is an early write cycle and the data output will remain high impedance for
.
, t
RWD
RAC(max)
RAC(max)
t
RWD(min)
can be met. t
can be met, t
, t
AWD
t
AWD(min)
RCD(max)
RAD(max)
, then the cycle is a read-write cycle and the
is specified as a reference point.
is specified as a reference point only. If t
AA
.
E
OH
or V
OL
.
RAD

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