tc58dvm72f1ft00 TOSHIBA Semiconductor CORPORATION, tc58dvm72f1ft00 Datasheet - Page 17

• Manufacturer Part Number: tc58dvm72f1ft00
• Description: 128-mbit 16m X 8 Bits/8m X 16bits Cmos Nand E2prom
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Schematic Cell Layout and Address Assignment
32768 pages
32768 pages
1024 blocks
1024 blocks
Table 1. Addressing
First cycle
Second cycle
Third cycle
* : A8 is automatically set to Low or High by a 00H command or a 01H command.
*
The Program operation works on page units while the Erase operation works on block units.
I/O8 must be set to Low in the third cycle.
I/O9-16 should be low when address is input.
Figure 2-2. x16 Schematic Cell Layout
Figure 2. Schematic Cell Layout
512
256
528
264
I/O8
A16
A7
*L
16
I/O7
A15
A23
8
A6
I/O6
A14
A22
16I/O
A5
8I/O
I/O8
I/O16
32 pages
32 pages
1 block
1 block
I/O5
A13
A21
A4
I/O1
I/O1
TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
I/O4
A12
A20
A3
for main memory storage and 16 bytes are for redundancy
or for other uses.
used for main memory storage and 8 words are for
redundancy or for other uses.
consecutive clock cycles, as shown in Table 1.
I/O3
A11
A19
A2
A page consists of 528 bytes in which 512 bytes are used
A page consists of 264 words in which 256 words are
An address is read in via the I/O port over three
1 page
1 block
Capacity
1 page
1 block
Capacity
I/O2
A10
A18
A1
528 bytes
264 words
528 bytes u 32 pages
264 words u 32 pages
I/O1
528 bytes u 32 pages u 1024 blocks
264 words u 32 pages u 1024 blocks
A17
A0
A9
A0~A7:
A9~A23: Page address
A14~A23: Block address
A9~A13: NAND address in block
Column address
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(16K  512) bytes
(8K  256) words