stk16ca8 Simtek Corporation, stk16ca8 Datasheet - Page 8

• Manufacturer Part Number: stk16ca8
• Description: 128k Autostoreplus?? Nvsram Quantumtrap?? Cmos Nonvolatile Static
• Manufacturer: Simtek Corporation

STK16CA8
September 2003
The STK16CA8 has two separate modes of opera-
tion:
mode, the memory operates as a standard fast
static
from
operation) or from the nonvolatile elements to
(the
tions are disabled.
SRAM READ
The STK16CA8 performs a
and G are low and W is high. The address specified
on pins A
bytes will be accessed. When the
by an address transition, the outputs will be valid
after a delay of t
initiated by E or G, the outputs will be valid at t
at t
outputs will repeatedly respond to address changes
within the t
sitions on any control input pins, and will remain valid
until new output data appears or until E or G is
brought high, or W is brought low.
SRAM WRITE
A
low. The address inputs must be stable prior to
entering the
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ
ten into the memory if it is valid t
of a W controlled
E controlled
It is recommended that G be kept high during the
entire
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
AutoStorePlus™ OPERATION
The STK16CA8’s automatic
is completely transparent to the system. The
AutoStore™ initiation takes less than 500ns when
power is lost (V
depends only on its internal capacitor for
completion.
In order to prevent unneeded
automatic
WRITE
GLQV
RECALL
SRAM
SRAM
RAM
WRITE
, whichever is later (
cycle is performed whenever E and W are
0-16
. In nonvolatile mode, data is transferred
AVQV
STORE
to the nonvolatile elements (the
mode and nonvolatile mode. In
WRITE
determines which of the 131,072 data
WRITE
cycle to avoid data bus contention on
operation). In this mode
access time without the need for tran-
CC
AVQV
WRITE
s will be ignored unless at least
< V
.
(
cycle and must remain stable
READ
SWITCH
or t
READ
) at which point the part
cycle #1). If the
DVEH
READ
STORE
WLQZ
before the end of an
cycle #2). The data
DVWH
STORE
after W goes low.
cycle whenever E
READ
on power-down
DEVICE OPERATION
before the end
0-7
SRAM
will be writ-
operations,
is initiated
READ
STORE
STORE
ELQV
SRAM
SRAM
func-
or
is
8
one
recent
STORE
or not a
POWER-UP RECALL
During power up, or after any low-power condition
(V
latched. When V
voltage of V
be initiated and will take t
If the STK16CA8 is in a
power-up
or W must be brought high and then low for a write
to initiate.
SOFTWARE NONVOLATILE STORE
The STK16CA8 software
executing sequential
six specific address locations. During the
cycle an erase of the previous nonvolatile data is
first performed, followed by a program of the nonvol-
atile elements. The program operation copies the
SRAM
cycle is initiated, further input and output are dis-
abled until the cycle is completed.
Because a sequence of
addresses is used for
tant that no other
vene in the sequence, or the sequence will be
aborted and no
To initiate the software
READ
The software sequence must be clocked with E con-
trolled
Once the sixth address in the sequence has been
entered, the
chip will be disabled. It is important that
and not
it is necessary that G be low for the sequence to be
CCX
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
WRITE
Document Control # ML0023 rev 0.1
< V
sequence must be performed:
data into nonvolatile memory. Once a
READ
STORE
cycles are performed regardless of whether
WRITE
WRITE
SWITCH
RECALL
operation has taken place since the most
SWITCH
s.
STORE
), an internal
or
operation has taken place.
cycles be used in the sequence, and
STORE
CC
, a
, the
RECALL
READ
once again exceeds the sense
4E38 (hex)
B1C7 (hex)
83E0 (hex)
7C1F (hex)
703F (hex)
8FC0 (hex)
RECALL
E
cycle will commence and the
WRITE
STORE
or
controlled
STORE
RESTORE
WRITE
STORE
or
RECALL
cycle. Software initiated
RECALL
WRITE
cycle will automatically
READ
will be inhibited and E
initiation, it is impor-
to complete.
cycle, the following
state at the end of
cycle is initiated by
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
READ
will take place.
s from specific
accesses inter-
request will be
READ
cycles from
STORE
STORE
cycles