at26df081a ATMEL Corporation, at26df081a Datasheet
at26df081a
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at26df081a Summary of contents
Page 1
... Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options – 8-lead SOIC (150-mil and 200-mil wide) 1. Description The AT26DF081A is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer-based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The ...
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... Specifically designed for use in 3-volt systems, the AT26DF081A supports read, program, and erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing. ...
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... CC voltages may produce spurious results and should not be attempted. 8-SOIC Top View VCC HOLD SCK GND AT26DF081A Asserted State Type Low Input Input Input Output Low Input CC Low Input “Hold” whenever CC Power Power 3 ...
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... WP 4. Memory Array To provide the greatest flexibility, the memory array of the AT26DF081A can be erased in four levels of granularity including a full chip erase. In addition, the array has been divided into phys- ical sectors of various sizes, of which each sector can be individually protected from program and erase operations ...
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... AT26DF081A Page Program Detail 1-256 Byte Page Program Page Address (02h Command) Range 256 Bytes 0FFFFFh – 0FFF00h 256 Bytes 0FFEFFh – 0FFE00h 256 Bytes 0FFDFFh – ...
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... Device Operation The AT26DF081A is controlled by a set of instructions that are sent from a host controller, com- monly referred to as the SPI Master. The SPI Master communicates with the AT26DF081A via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO) ...
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... Use Write Status Register command 3Ch 0011 1100 3 05h 0000 0101 0 01h 0000 0001 0 9Fh 1001 1111 0 B9h 1011 1001 0 ABh 1010 1011 0 AT26DF081A Dummy Bytes Data Bytes ...
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... Figure 7-1. Read Array – 0Bh Opcode SCK OPCODE MSB HIGH-IMPEDANCE SO Figure 7-2. Read Array – 03h Opcode CS SCK SI MSB HIGH-IMPEDANCE SO AT26DF081A ADDRESS BITS A23- ...
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... WEL bit in the Status Register will be reset back to the logical “0” state. 3600F–DFLASH–03/07 “Write Enable” on page 15 command description) to set the Write time to determine if the data bytes have finished programming AT26DF081A . PP “Protect Sector” ...
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... When using the Sequential Program mode, all address locations to be programmed must be in the erased state. Before the Sequential Program mode can first be entered, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Reg- ister to a logical “1” state. AT26DF081A ...
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... The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly programming error arises, it will be indicated by the EPE bit in the Status Register. 3600F–DFLASH–03/07 AT26DF081A . For each program cycle time to determine if the byte has fin- ...
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... CS pin is deas- serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase operation will be performed. AT26DF081A 12 Status Register Read ...
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... At BLKE Block Erase SCK OPCODE MSB HIGH-IMPEDANCE SO AT26DF081A ADDRESS BITS A23- MSB 31 A ...
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... The device also incorporates an intelligent erasing algorithm that can detect when a byte loca- tion fails to erase properly erase error occurs, it will be indicated by the EPE bit in the Status Register. Figure 8-6. AT26DF081A 14 . CHPE time to determine if the device has finished erasing. At ...
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... CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change. 3600F–DFLASH–03/07 Write Enable SCK OPCODE MSB HIGH-IMPEDANCE SO AT26DF081A ...
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... If the Sector Protection Registers are locked, then any attempts to issue the Protect Sector command will be ignored, and the device will reset the WEL bit in the Status Reg- ister back to a logical “0” and return to the idle state once the CS pin has been deasserted. AT26DF081A 16 Write Disable ...
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... HIGH-IMPEDANCE SO Unprotect Sector SCK OPCODE MSB MSB HIGH-IMPEDANCE SO AT26DF081A ADDRESS BITS A23- Table 9-1 for Sector Protection ...
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... Global Unprotect, the same WP and SPRL conditions must be met but the system must write a logical “0” to bits and 2 of the Status Register. necessary for a Global Protect or Global Unprotect to be performed. AT26DF081A 18 page 26 for command execution details). The Write Status Register com- ...
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... SPRL bit can be changed back from a 1 since the WP ↕ pin is HIGH. To perform a Global Protect/Unprotect, the Write Status Register command must be issued again after the SPRL bit has been changed from AT26DF081A New SPRL Value ...
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... Figure 9-5. CS SCK SI SO AT26DF081A 20 for details on the Status Register format and what values can be Read Sector Protection Register – Output Data Sector Protection Register Value Sector Protection Register value is 0 (sector is unprotected). Sector Protection Register value is 1 (sector is protected). ...
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... Status Register. Tables 9-4 and 9-5 Table 9-4. Note: 3600F–DFLASH–03/07 detail the various protection and locking states of the device. Sector Protection Register States Sector Protection Register WP X (Don't Care) 1. “n” represents a sector number AT26DF081A n(1) 0 Unprotected 1 Protected Sector n(1) 21 ...
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... Table 9- AT26DF081A 22 Hardware and Software Locking SPRL Locking SPRL Change Allowed 0 Can be modified from Hardware 1 Locked Locked 0 Can be modified from Software 1 Can be modified from Locked Sector Protection Registers Unlocked and modifiable using the Protect and Unprotect Sector commands ...
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... Sector Protection Registers to determine which R sectors are protected. 10 Reserved for future use. All sectors are software protected (all Sector 11 Protection Registers are 1 – default). 0 Device is not write enabled (default Device is write enabled. 0 Device is ready Device is busy with an internal operation. AT26DF081A 23 ...
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... Protect Sector command or the Global Protect feature. If the SWP bits indicate that some of the sectors have been protected, then the individual Sector Pro- tection Registers can be read with the Read Sector Protection Registers command to determine which sectors are in fact protected. AT26DF081A 24 3600F–DFLASH–03/07 ...
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... SI SO 3600F–DFLASH–03/ OPCODE MSB STATUS REGISTER DATA HIGH-IMPEDANCE MSB AT26DF081A STATUS REGISTER DATA MSB MSB 25 ...
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... WEL bit in the Status Register will be reset back to the logical “0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted. Table 10-2. Bit 7 SPRL Figure 10-2. Write Status Register AT26DF081A 26 page 18 for more details. Write Status Register Format Bit 6 ...
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... JEDEC Assigned Code Density Code Product Version Code AT26DF081A Hex Bit 0 Value Details 1Fh JEDEC Code: 0001 1111 (1Fh for Atmel) 1 Family Code: 010 (AT26DFxxx series) 45h Density Code: 00101 (8-Mbit) 1 MLC Code: 000 (1-bit/cell technology) 01h ...
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... The Deep Power-down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. The Deep Power-down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the Deep Power-down mode. AT26DF081A ...
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... Standby Mode Current Deep Power-Down Mode Current and return to the standby mode. After the device RDPD SCK OPCODE MSB HIGH-IMPEDANCE SO Active Current I CC Deep Power-Down Mode Current AT26DF081A t EDPD t RDPD Standby Mode Current 29 ...
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... If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state. Figure 11-4. Hold Mode CS SCK HOLD AT26DF081A 30 Hold Hold Hold 3600F–DFLASH–03/07 ...
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... This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT26DF081A -40°C to 85°C 2.7V to 3.6V Min Typ Max 25 ...
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... Chip Select High to Standby Mode RDPD Notes: 1. Not 100% tested (value guaranteed by design and characterization load at 70 MHz load at 66 MHz. 3. Only applicable as a constraint for the Write Status Register command when SPRL = 1 AT26DF081A 32 Min Max Units 70 MHz 33 MHz 6 ...
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... Input Test Waveforms and Measurement Levels < (10 12.8 Output Test Load 3600F–DFLASH–03/07 Min 4 Kbytes 32 Kbytes 64 Kbytes Min 50 1.5 2.4V AC 1.5V DRIVING LEVELS 0.45V DEVICE UNDER TEST AT26DF081A Typ Max Units 1 µs 50 200 250 600 ms 400 950 6 14 sec 200 ns Max Units µ ...
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... Figure 13-1. Serial Input Timing CS t CSLS SCK MSB HIGH-IMPEDANCE SO Figure 13-2. Serial Output Timing CS SCK Figure 13-3. HOLD Timing – Serial Input CS SCK HOLD SI HIGH-IMPEDANCE SO AT26DF081A 34 t CSLH t t SCKH SCKL t DH LSB HHH HLS t HLH t CSH t ...
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... Figure 13-5. WP Timing for Write Status Register Command When SPRL = WPS WP SCK SI 0 MSB OF WRITE STATUS REGISTER OPCODE HIGH-IMPEDANCE SO 3600F–DFLASH–03/07 t HLS t HLH t t HLQZ HHQX LSB OF WRITE STATUS REGISTER DATA BYTE AT26DF081A t HHS WPH MSB MSB OF NEXT OPCODE 35 ...
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... SCK AT26DF081A-SSU 70 AT26DF081A-SU 8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8S2 8-lead, 0.209” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) AT26DF081A 36 Package 8S1 8S2 Package Type Operation Range Industrial (-40°C to 85°C) ...
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... Colorado Springs, CO 80906 R 3600F–DFLASH–03/ TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) AT26DF081A Ø Ø END VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM A1 0.10 – ...
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... It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. 4. Determines the true geometric position. 5. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. 2325 Orchard Parkway San Jose, CA 95131 R AT26DF081A TOP VIEW ...
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... Reduced typical page program time from 3 1 Reduced typical byte program time from 12 µ µs - Reduced 32KB typical block erase time from 350 ms to 250 ms - Reduced 64KB typical block erase time from 700 ms to 400 ms - Reduced typical Chip Erase time from 10 sec to 6 sec AT26DF081A Section 12.5 12.5. 39 ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2007 Atmel Corporation. All rights reserved. Atmel istered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Operations Memory ...