w942508ch Winbond Electronics Corp America, w942508ch Datasheet - Page 28

• Manufacturer Part Number: w942508ch
• Description: 8m X 4 Banks X 8 Bit Ddr Sdram
• Manufacturer: Winbond Electronics Corp America

(4) DLL Reset bit (A8)
(5) Mode Register /Extended Mode register change bits (BS0, BS1)
(6) Extended Mode Register field
(3) CAS Latency field (A6 to A4)
(7) Reserved field
x
x
1) DLL Switch field (A0)
2) Output Driver Size Control field (A1)
This field specifies the number of clock cycles from the assertion of the Read command to the
first data read. The minimum values of CAS Latency depends on the frequency of CLK.
This bit is used to reset DLL. When the A8 bit is "1", DLL is reset.
These bits are used to select MRS/EMRS.
This bit is used to select DLL enable or disable
This bit is used to select Output Driver Size, both Full strength and Half strength are based on
JEDEC standard.
Test mode entry bit (A7)
Reserved bits (A9, A10, A11, A12)
This bit is used to enter Test mode and must be set to "0" for normal operation.
These bits are reserved for future operations. They must be set to "0" for normal operation.
BS1
A6
A0
A1
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
BS0
A5
0
0
1
1
0
0
1
1
0
1
x
OUTPUT DRIVER
Disable
Enable
DLL
Half Strength
- 28 -
Full Strength
A4
0
1
0
1
0
1
0
1
Extended MRS Cycle
Regular MRS Cycle
Reserved
CAS LATENCY
A12-A0
Reserved
Reserved
Reserved
Reserved
Reserved
2.5
2
3
W942508CH