m24256-br STMicroelectronics, m24256-br Datasheet - Page 25

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m24256-br

Manufacturer Part Number
m24256-br
Description
512 Kbit And 256 Kbit Serial I2c Bus Eeprom With Three Chip Enable Lines
Manufacturer
STMicroelectronics
Datasheet

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M24512-W, M24512-R, M24512-HR, M24256-BW, M24256-BR
Table 14.
1. Values recommended by the I²C-bus Fast-Mode specification.
2. Characterized only, not tested in production.
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
4. t
5. For a reStart condition, or following a Write cycle.
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
C
CHCL
CLCH
XH1XH2
XL1XL2
DL1DL2
DXCX
CLDX
CLQX
CLQV
CHDX
DLCL
CHDH
DHDL
W
NS
Symbol
rising edge of SDA.
that the R
(2)
CLQV
(3)(4)
(5)
(1)
(2)
(1)
is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8V
bus
1 MHz AC characteristics (M24xxx-HR, see
f
t
t
t
t
t
t
t
t
t
t
t
t
SCL
HIGH
LOW
R
F
F
SU:DAT
SU:STA
HD:STA
SU:STO
BUF
WR
× C
HD:DAT
Alt.
t
t
DH
AA
bus
time constant is less than 150 ns (as specified in
Clock frequency
Clock pulse width high
Clock pulse width low
Input signal rise time
Input signal fall time
SDA (out) fall time
Data in setup time
Data in hold time
Data out hold time
Clock low to next data valid (access time)
Start condition setup time
Start condition hold time
Stop condition setup time
Time between Stop condition and next
Start condition
Write time
Pulse width ignored (input filter on SCL
and SDA)
Test conditions specified in
Parameter
Table 8
Table 8
Figure
and
0
300
400
20
20
20
80
0
50
50
250
250
250
500
-
-
Min.
4).
Table
DC and AC parameters
9)
1
-
-
300
300
100
-
-
-
500
-
-
-
-
5
50
Max.
CC
, assuming
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
Unit
25/35

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