m24c04-w STMicroelectronics, m24c04-w Datasheet - Page 16

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m24c04-w

Manufacturer Part Number
m24c04-w
Description
16kbit, 8kbit, 4kbit, 2kbit And 1kbit Serial I2c Bus Eeprom
Manufacturer
STMicroelectronics
Datasheet

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Device operation
3.7
3.7.1
16/34
Figure 9.
1. The seven most significant bits of the device select code of a Random Read (in the 1
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
The device has an internal address counter which is incremented each time a byte is read.
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure
condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.
be identical.
CURRENT
ADDRESS
READ
RANDOM
ADDRESS
READ
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
9) but without sending a Stop condition. Then, the bus master sends another Start
Read mode sequences
DEV SEL *
DEV SEL *
DEV SEL
DEV SEL
ACK
DATA OUT N
R/W
R/W
R/W
R/W
ACK
ACK
ACK
ACK
NO ACK
DATA OUT 1
BYTE ADDR
BYTE ADDR
DATA OUT
M24C16, M24C08, M24C04, M24C02, M24C01
NO ACK
ACK
ACK
ACK
DEV SEL *
DEV SEL *
ACK
ACK
ACK
R/W
R/W
DATA OUT N
DATA OUT 1
DATA OUT
st
and 3
NO ACK
NO ACK
rd
ACK
bytes) must
AI01942

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