is42s32200c1 Integrated Silicon Solution, Inc., is42s32200c1 Datasheet
is42s32200c1
Manufacturer Part Number
is42s32200c1
Description
512k Bits X 32 Bits X 4 Banks 64-mbit Synchronous Dynamic Ram
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet
1.IS42S32200C1.pdf
(1 pages)
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IS42S32200C1-DIE
512K Bits x 32 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEATURES
• Clock frequency: 166, 143 MHz
• Fully synchronous; all signals referenced to a
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length:
• Programmable burst sequence:
• Self refresh modes
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
• Burst termination by burst stop and precharge
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. 00A
05/24/05
PIN DESCRIPTIONS
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
A0-A10
BA0, BA1
DQ0 to DQ31
CLK
CKE
CS
RAS
CAS
WE
DQM0 to DQM3
positive clock edge
(1, 2, 4, 8, full page)
Sequential/Interleave
operations capability
command
Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
Write Enable
Input/Output Mask
1-800-379-4774
OVERVIEW
ISSI
organized as 524,288 bits x 32-bit x 4-bank for improved
performance. The synchronous DRAMs achieve high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
Note: This is a summary datasheet specific to the die
format. Please refer to the IS42S32200C1 for complete
device specification.
KEY TIMING PARAMETERS
BONDING DIAGRAM
V
VSS
V
V
NC
Parameter
Clock Cycle Time
Clock Frequency
Access Time from Clock
DD
DDQ
SSQ
's 64Mb Synchronous DRAM IS42S32200C1 is
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
Power
Ground
Power Supply for DQ Pin
Ground for DQ Pin
No Connection
PRELIMINARY INFORMATION
ISSI
May 2005
167
100
5.5
7.5
10
-6
6
143
100
5.5
10
-7
7
8
MHz
MHz
Unit
ns
ns
ns
ns
®
1
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