is42s16100f-75tl Integrated Silicon Solution, Inc., is42s16100f-75tl Datasheet - Page 7

• Manufacturer Part Number: is42s16100f-75tl
• Description: 512k Words X 16 Bits X 2 Banks 16mb Sdram
• Manufacturer: Integrated Silicon Solution, Inc.

IS42S16100F, IS42VS16100F
IS42S16100F DC ELECTRICAL CHARACTERISTICS
(Recommended Operation Conditions unless otherwise noted.)
Notes:
1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time in-
2. Icc
3. Inputs changed once every two clocks.
4. Not all parameters are tested at the wafer level, but the parameters have been previously characterized.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
08/22/08
Symbol Parameter
i
i
I
i
I
i
I
i
I
i
i
i
i
cc1
cc2p
cc2ps
cc2n
cc2ns
cc3P
cc3Ps
cc3n
cc3ns
cc4
cc5
cc6
cc7
creases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between V
to suppress power supply voltage noise (voltage drops) due to these transient currents.
1
and Icc
Operating Current
Precharge Standby Current
(In Power-Down Mode)
Precharge Standby Current
(In Power-Down and
Clock Suspend Mode)
Precharge Standby Current
(In Non Power-Down Mode)
Precharge Standby Current
(In Non Power-Down and
Clock Suspend Mode)
Active Standby Current
(In Power-Down Mode)
Active Standby Current
(In Power-Down and
Clock Suspend Mode)
Active Standby Current
(In Non Power-Down Mode)
Active Standby Current
(In Non Power-Down and
Clock Suspend Mode)
Operating Current
(In Burst Mode)
Auto-Refresh Current
Self-Refresh Current
Deep Power Down Current CKE ≤ 0.2V
4
depend on the output load. The maximum values for Icc
(1,3)
(1,2)
(3)
(3)
Test Condition
One Bank Operation, CAS Latency = 3
Burst Length=1
t
I
CKE ≤ V
CKE ≤ V
CLK ≤ V
CKE ≥ V
CS ≥ V
CKE ≥ V
CLK ≤ V
CKE ≤ V
CKE ≤ V
CLK ≤ V
CKE ≥ V
CS ≥ V
CKE ≥ V
CLK ≤ V
Both Banks activated t
Page Burst
I
t
CKE ≤ 0.2V
rc
out
out
rc
≥ t
= t
= 0mA
= 0mA
rc
rc
ih
ih
il
il
il
il
il
il
ih
ih
il
il
ih
ih
(min)
(
(
(
min
min
min
(
(
(
(
(
(
(
(
max
(
(
(
(
min
min
min
min
max
max
max
max
max
max
max
)
)
)
) t
) t
) t
) t
) Inputs are stable
)
) Inputs are stable
) Inputs are stable
) t
) t
) t
) t
ck
ck
ck
ck
ck
ck
ck
ck
= t
= ∞
= t
= ∞
= t
= ∞
= t
= ∞
ck
ck
ck
ck
ck
(min)
(min)
(min)
(min)
1
= t
and Icc
(4)
ck
(
min
4
)
are obtained with the output open state.
Com.
Com.
Ind.
Ind.
dd
and Vss for each memory chip
170
170
120
35
20
55
30
10
—
—
-5
2
2
3
3
2
160
170
150
100
110
35
20
55
30
10
-6
2
2
3
3
2
140
160
130
35
20
55
30
70
90
10
-7
2
2
3
3
2
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
7