is62c5128bl Integrated Silicon Solution, Inc., is62c5128bl Datasheet - Page 9

• Manufacturer Part Number: is62c5128bl
• Description: 512k?x?8?high-speed?cmos?static?ram
• Manufacturer: Integrated Silicon Solution, Inc.

IS62C5128BL, IS65C5128BL
WRITE CYCLE NO. 2
WRITE CYCLE NO. 3
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
2. I/O will assume the High-Z state if OE
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/15/2010
ADDRESS
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
ADDRESS
D
D
OUT
WE
D
OE
CE
OUT
WE
D
OE
CE
IN
IN
LOW
LOW
LOW
t
SA
t
DATA UNDEFINED
SA
DATA UNDEFINED
(OE is HIGH During Write Cycle)
(OE is LOW During Write Cycle)
≥
V
ih
.
VALID ADDRESS
t
t
t
t
AW
HZWE
AW
HZWE
VALID ADDRESS
t
t
PWE1
WC
t
t
(1)
PWE2
(1,2)
WC
HIGH-Z
HIGH-Z
t
t
SD
SD
DATA
DATA
IN
IN
VALID
VALID
t
t
HD
HD
t
t
LZWE
LZWE
t
t
HA
HA
CE_WR2.eps
CE_WR3.eps
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