at28bv64 ATMEL Corporation, at28bv64 Datasheet - Page 4

• Manufacturer Part Number: at28bv64
• Description: 64k 8k X 8 Battery-voltage Parallel Eeproms
• Manufacturer: ATMEL Corporation

5. Device Operation
5.1
5.2
5.3
5.4
5.5
4
Read
Byte Write
READY/BUSY
DATA Polling
Write Protection
AT28BV64
The AT28BV64 is accessed like a Static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in a high impedance state whenever CE or OE is high. This dual line control
gives designers increased flexibility in preventing bus contention.
Writing data into the AT28BV64 is similar to writing into a Static RAM. A low pulse on the WE or
CE input with OE high and CE or WE low (respectively) initiates a byte write. The address loca-
tion is latched on the falling edge of WE (or CE); the new data is latched on the rising edge.
Internally, the device performs a self-clear before write. Once a byte write has been started, it
will automatically time itself to completion. Once a programming operation has been initiated and
for the duration of t
Pin 1 is an open drain READY/BUSY output that can be used to detect the end of a write cycle.
RDY/BUSY is actively pulled low during the write cycle and is released at the completion of
the write. The open drain connection allows for OR-tying of several devices to the same
RDY/BUSY line.
The AT28BV64 provides DATA Polling to signal the completion of a write cycle. During a write
cycle, an attempted read of the data being written results in the complement of that data for I/O
(the other outputs are indeterminate). When the write cycle is finished, true data appears on all
outputs.
Inadvertent writes to the device are protected against in the following ways: (a) V
V
reached 2.0V the device will automatically time out 10 ms (typical) before allowing a byte write;
and (c) Write Inhibit – holding any one of OE low, CE high or WE high inhibits byte write cycles.
CC
is below 1.8V (typical) the write function is inhibited; (b) V
WC
, a read operation will effectively be a polling operation.
CC
power on delay – once V
0493C–PEEPR–08/07
CC
sense – if
CC
has
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