at49sv802a ATMEL Corporation, at49sv802a Datasheet - Page 6

• Manufacturer Part Number: at49sv802a
• Description: 8-megabit 512k X 16/ 1mx8 1.8-volt Only Flash Memory
• Manufacturer: ATMEL Corporation

4.6
4.6.1
4.6.2
6
Program/Erase Status
AT49SV802A(T)
Data Polling
Toggle Bit
The device provides several bits to determine the status of a program or erase operation: I/O2,
I/O5, I/O6 and I/O7. The
the function of these bits. To provide greater flexibility for system designers, the
AT49SV802A(T) contains a programmable configuration register. The configuration register
allows the user to specify the status bit operation. The configuration register can be set to one of
two different values, “00” or “01”. If the configuration register is set to “00”, the part will automati-
cally return to the read mode after a successful program or erase operation. If the configuration
register is set to a “01”, a Product ID Exit command must be given after a successful program or
erase operation before the part will return to the read mode. It is important to note that whether
the configuration register is set to a “00” or to a “01”, any unsuccessful program or erase opera-
tion requires using the Product ID Exit command to return the device to read mode. The default
value (after power-up) for the configuration register is “00”. Using the four-bus cycle Set Config-
uration Register command as shown in the
of the configuration register can be changed. Voltages applied to the RESET pin will not alter the
value of the configuration register. The value of the configuration register will affect the operation
of the I/O7 status bit as described below.
The AT49SV802A(T) features Data Polling to indicate the end of a program cycle. If the status
configuration register is set to a “00”, during a program cycle an attempted read of the last
byte/word loaded will result in the complement of the loaded data on I/O7. Once the program
cycle has been completed, true data is valid on all outputs and the next cycle may begin. During
a chip or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the
program or erase cycle has completed, true data will be read from the device. Data Polling may
begin at any time during the program cycle. Please see
details.
If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the
device is actively programming or erasing data. I/O7 will go high when the device has completed
a program or erase operation. Once I/O7 has gone high, status information on the other pins can
be checked.
The Data Polling status bit must be used in conjunction with the erase/program and V
bit as shown in the algorithm in
In addition to Data Polling the AT49SV802A(T) provides another method for determining the end
of a program or erase cycle. During a program or erase operation, successive attempts to read
data from the memory will result in I/O6 toggling between one and zero. Once the program cycle
has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may
begin at any time during a program cycle. Please see
details.
The toggle bit status bit should be used in conjunction with the erase/program status bit as
shown in the algorithm in
“Status Bit Table” on page 12
Figures 4-3 and 4-4
Figures 4-1 and 4-2
“Command Definition Table” on page
on
page
on
11.
page
and the following four sections describe
“Status Bit Table” on page 12
“Status Bit Table” on page 12
10.
3522E–FLASH–10/07
13, the value
PP
for more
for more
status