at49f2048 ATMEL Corporation, at49f2048 Datasheet - Page 4

• Manufacturer Part Number: at49f2048
• Description: 2-megabit 128k X 16 5-volt Only Flash Memory
• Manufacturer: ATMEL Corporation

gram or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result
in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any time
during a program cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49F2048 in
Command Definition (in Hex)
Notes:
Absolute Maximum Ratings*
4
Command
Sequence
Read
Chip Erase
Sector Erase
Word Program
Boot Block
Lockout
Product ID
Entry
Product ID
Exit
Product ID
Exit
Temperature Under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
(3)
(3)
(2)
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex)
2. The 8K word boot sector has the address range 00000H to 01FFFH.
3. Either one of the Product ID Exit commands can be used.
4. SA = sector addresses:
5. When the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase
SA = 03XXX for PARAMETER BLOCK 1
SA = 05XXX for PARAMETER BLOCK 2
SA = 1FXXX for MAIN MEMORY ARRAY
together (from the same sector erase command). Once the boot region has been protected, only the main memory array
sector will erase when its sector erase command is issued.
Cycles
Bus
1
6
6
4
6
3
3
1
AT49F2048
Addr
Addr
5555
5555
5555
5555
5555
5555
xxxx
1st Bus
Cycle
Data
D
AA
AA
AA
AA
AA
AA
F0
OUT
(1)
Addr
2AAA
2AAA
2AAA
2AAA
2AAA
2AAA
2nd Bus
Cycle
CC
+ 0.6V
Data
55
55
55
55
55
55
Addr
5555
5555
5555
5555
5555
5555
3rd Bus
the following ways: (a) V
ical), the program function is inhibited. (b) V
delay: once V
device will automatically time out 10 ms (typical) before
programming. (c) Program inhibit: holding any one of OE
low, CE high or WE high inhibits program cycles. (d) Noise
filter: pulses of less than 15 ns (typical) on the WE or CE
inputs will not initiate a program cycle.
Cycle
*NOTICE:
Data
80
80
A0
80
90
F0
Addr
5555
5555
5555
Addr
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
4th Bus
CC
Cycle
has reached the V
Data
D
AA
AA
AA
IN
CC
sense: if V
Addr
2AAA
2AAA
2AAA
5th Bus
Cycle
Data
55
55
55
CC
CC
is below 3.8V (typ-
sense level, the
SA
Addr
5555
5555
CC
(4)(5)
6th Bus
Cycle
power on
Data
10
30
40