at49bv4096 ATMEL Corporation, at49bv4096 Datasheet - Page 4

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at49bv4096

Manufacturer Part Number
at49bv4096
Description
4-megabit 256k X 16 3-volt Only Flash Memory
Manufacturer
ATMEL Corporation
Datasheet

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HARDWARE DATA PROTECTION: Hardware features
p r o t e c t a g a i n s t i n a d v e r t e n t p r o g r a m s t o t h e
AT49BV4096/LV4096 in the following ways: (a) V
if V
ited. (b) V
V
ms (typical) before programming. (c) Program inhibit: hold-
ing any one of OE low, CE high or WE high inhibits pro-
gram cycles. (d) Noise filter: pulses of less than 15 ns
Command Definition (in Hex)
Notes:
Absolute Maximum Ratings*
4
Command
Sequence
Read
Chip Erase
Sector Erase
Word
Program
Boot Block
Lockout
Product ID
Entry
Product ID
Exit
Product ID
Exit
Operating Temperature ................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage............................................. 6.6V
DC Output Current...................................................... 25.0 mA
CC
CC
sense level, the device will automatically time out 10
(3)
(3)
is below 1.8V (typical), the program function is inhib-
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).
2. The 8K word boot sector has the address range 00000H to 01FFFH.
3. Either one of the Product ID Exit commands can be used.
4. SA = sector addresses
5. When the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase.
(2)
CC
SA = 03XXX for PARAMETER BLOCK 1
SA = 05XXX for PARAMETER BLOCK 2
SA = 1FXXX for MAIN MEMORY ARRAY
power on delay: once V
AT49BV/LV4096
Cycles
Bus
1
6
6
4
6
3
3
1
Addr
5555
5555
5555
5555
5555
5555
Addr
xxxx
1st Bus
Cycle
Data
D
AA
AA
AA
AA
AA
AA
F0
OUT
CC
has reached the
2AAA
2AAA
2AAA
2AAA
2AAA
2AAA
Addr
(1)
2nd Bus
Cycle
CC
Data
55
55
55
55
55
55
sense:
Addr
5555
5555
5555
5555
5555
5555
3rd Bus
Cycle
(typical) on the WE or CE inputs will not initiate a program
cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V
power supply, the address inputs and control inputs (OE,
CE, and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to V
*NOTICE:
Data
A0
F0
80
80
80
90
Addr
5555
5555
5555
Addr
4th Bus
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Cycle
Data
D
AA
AA
AA
IN
2AAA
2AAA
2AAA
Addr
5th Bus
Cycle
CC
Data
55
55
55
+ 0.6V.
SA
Addr
5555
5555
(4)(5)
6th Bus
Cycle
Data
30
10
40

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