74ALVCH16374TX Fairchild Semiconductor, 74ALVCH16374TX Datasheet
74ALVCH16374TX
Specifications of 74ALVCH16374TX
Related parts for 74ALVCH16374TX
74ALVCH16374TX Summary of contents
Page 1
... MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 1) Note 1: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © 2002 Fairchild Semiconductor Corporation Features 1.65V to 3.6V V supply operation CC 3 ...
Page 2
Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW Clock Pulse Input n I –I Bushold Inputs –O Outputs ...
Page 3
Functional Description The 74ALVCH16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte func- tioning identically, but independent of the other. The control pins can be shorted together ...
Page 4
Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 3) 0. Input Diode Current ( Output Diode Current (I ) ...
Page 5
AC Electrical Characteristics Symbol Parameter V CC Min f Clock Frequency CLOCK t Pulse Width 3 Setup Time 1 Hold Time 0 Maximum Clock Frequency 150 MAX Propagation Delay 1.0 PHL ...
Page 6
AC Loading and Waveforms FIGURE 1. AC Test Circuit (Input Characteristics: f Symbol 3. FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE ...
Page 7
Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...