at88sc0104c ATMEL Corporation, at88sc0104c Datasheet - Page 21

• Manufacturer Part Number: at88sc0104c
• Description: Cryptomemory Specification For Standard Mode Of Operation
• Manufacturer: ATMEL Corporation

5.3.8.1
5.3.8.2
5.3.8.3
5.3.8.4
5.3.8.5
5.3.9
5.3.9.1
5210A–SMIC–04/07
Access Registers
SME – Supervisor Mode Enable
UCR – Unlimited Checksum Reads
UAT – Unlimited Authentication Trials
ETA – Eight Trials Allowed
CS0 – CS3: Programmable Chip Select (only relevant in synchronous protocol)
PM(1:0) Password Mode
Asserting this bit (SME = “0”) enables supervisor mode for Write 7 password such that verifying
Write 7 password grants read and write accesses to all password sets and PACs. Verifying
Write 7 password does not grant access to other passwords when this bit is not asserted (SME
= “1”).
UCR is applicable under authentication and encryption modes of operation.
UAT is applicable under the authentication mode of operation.
Asserting this bit (ETA = “0”) extends the trials limit to 8 incorrect attempts to verify a password.
The password attempt counter (PAC) will decrement ($FF, $FE, $FC, $F8, $F0, $E0, $C0, $80,
$00) with each incorrect attempt. Disabling this bit (ETA = “1”) limits password verification trials
to only four incorrect attempts ($FF, $EE, $CC, $88, $00). The ETA bit also has an application
in the authentication mode of operation.
The four most significant bits (b4 – b7) of every command comprise the Chip Select Address. All
CryptoMemory devices will respond to the default Chip Select Address of $B (1011). Each
device also responds to a second Chip Select Address programmed into CS0-CS3 of the Device
Configuration Register. By programming each device to a unique Chip Select Address, it is pos-
sible to connect up to 15 devices on the same Serial Data bus and communicate individually to
each. Global communications to all devices sharing the bus is accomplished using the default
Chip Select Address $B.
Four, eight, or sixteen 8-bit access registers allow personalization of the device. Each access
register works in conjunction with a Password/Key register to define the security settings for
each individual zone of the user memory. Values in the access registers take immediate effect
after programming. The default value for each bit is “1”.
Table 5-3.
Table 5-4.
Bit 7
PM1
PM0
1
1
0
AT88SC0104/0204/0404/0808/1616/3216/6416/12816/25616C
PM0
Bit 6
Access Register
Password Mode
PM1
1
0
*
Bit 5
AM1
Read and Write Passwords required
Write Password required
No Password required
AM0
Bit4
Access
Bit 3
ER
WLM
Bit 2
MDF
Bit 1
PGO
Bit 0
17