at25040 ATMEL Corporation, at25040 Datasheet - Page 5

• Manufacturer Part Number: at25040
• Description: Spi Serial Eeproms 1k 128 X 8 2k 256 X 8 4k 512 X 8
• Manufacturer: ATMEL Corporation

Serial Interface
Description
0606M–SEEPR–06/03
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25010/020/040
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25010/020/040 has separate pins designated for
data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
The op-code also contains address bit A8 in both the READ and WRITE instructions.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25010/020/040, and the serial output pin (SO) will remain in a high impedance state
un til the falling edge of CS is de tected a gain. This will reinitialize the serial
communication.
CHIP SELECT: The AT25010/020/040 is selected when the CS pin is low. When the
device is not selected, data will not be accepted via the SI pin, and the serial output pin
(SO) will remain in a high impedance state.
H O LD : Th e H O LD p in is u se d in co n jun ctio n w it h the C S pin to s e le ct th e
AT25010/020/040. When the device is selected and a serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without
resetting the serial sequence. To pause, the HOLD pin must be brought low while the
SCK pin is low. To resume serial communication, the HOLD pin is brought high while the
SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored
while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations
when held high. When the WP pin is brought low, all write operations are inhibited.
WP going low while CS is still low will interrupt a write to the AT25010/020/040. If the
internal write cycle has already been initiated, WP going low will have no effect on any
write operation.
AT25010/020/040
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