at25020a ATMEL Corporation, at25020a Datasheet - Page 8

• Manufacturer Part Number: at25020a
• Description: Spi Serial Eeprom 1k 128x8 2k 256x8 4k 512x8
• Manufacturer: ATMEL Corporation

Functional
Description
8
AT25010A/020A/040A
The AT25010A/020A/040A is designed to interface directly with the synchronous serial
peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers.
The AT25010A/020A/040A utilizes an 8-bit instruction register. The list of instructions
and their operation codes are contained in Figure 5. All instructions, addresses, and
data are transferred with the MSB first and start with a high-to-low CS transition.
Table 5. Instruction Set for the AT25010A/020A/040A
Note:
WRITE ENABLE (WREN): The device will power up in the write disable state when V
is applied. All programming instructions must therefore be preceded by a Write Enable
instruction. The WP pin must be held high during a WREN instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write
Disable instruction disables all programming modes. The WRDI instruction is indepen-
dent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides
access to the status register. The read/busy and write enable status of the device can
be determined by the RDSR instruction. Similarly, the block write protection bits indicate
the extent of protection employed. These bits are set by using the WRSR instruction.
Table 6. Status Register Format
Table 7. Read Status Register Bit Definition
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select
one of four levels of protection. The AT25010A/020A/040A is divided into four array seg-
ments. One-quarter, one-half, or all of the memory segments can be protected. Any of
Bit
Bit 0 (RDY)
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Bits 4–7 are “0”s when device is not in an internal write cycle.
Bits 0–7 are “1”s during an internal write cycle.
Instruction Name
Bit 7
X
WRITE
WREN
WRSR
RDSR
READ
WRDI
“A” represents MSB address bit A8.
Bit 6
X
Instruction Format
Bit 5
X
0000 X110
0000 X100
0000 X101
0000 X001
0000 A011
0000 A010
Definition
Bit 0 = “0” (RDY) indicates the device is ready. Bit 0 = “1”
indicates the write cycle is in progress.
Bit 1 = “0” indicates the device is not write enabled. Bit 1 = “1”
indicates the device is write enabled.
See Table 8.
See Table 8.
Bit 4
X
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
Bit 3
BP1
Bit 2
BP0
WEN
Bit 1
3348J–SEEPR–8/06
Bit 0
RDY
CC