at25020b-wwu11l ATMEL Corporation, at25020b-wwu11l Datasheet - Page 7

• Manufacturer Part Number: at25020b-wwu11l
• Description: Spi Serial Eeprom
• Manufacturer: ATMEL Corporation

8707B–SEEPR–3/10
3.
Functional Description
The AT25010B/020B/040B is designed to interface directly with the synchronous serial peripheral interface (SPI) of
the 6805 and 68HC11 series of microcontrollers.
The AT25010B/020B/040B utilizes an 8-bit instruction register. The list of instructions and their operation codes
are contained in
high-to-low CS transition.
Table 3-1.
Note:
WRITE ENABLE (WREN): The device will power up in the write disable state when V
ming instructions must therefore be preceded by a Write Enable instruction. The WP pin must be held high during
a WREN instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables
all programming modes. The WRDI instruction is independent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register.
The read/busy and write enable status of the device can be determined by the RDSR instruction. Similarly, the
block write protection bits indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 3-2.
Table 3-3.
Bit
Bit 0 (RDY)
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Bits 4–7 are “0”s when device is not in an internal write cycle.
Bits 0–7 are “1”s during an internal write cycle.
Instruction Name
Bit 7
X
WRITE
WREN
WRSR
RDSR
READ
WRDI
“A” represents MSB address bit A8.
Bit 6
Instruction Set for the AT25010B/020B/040B
Status Register Format
Read Status Register Bit Definition
X
Figure
Definition
Bit 0 = “0” (RDY) indicates the device is ready.
Bit 0 = “1” indicates the write cycle is in progress.
Bit 1 = “0” indicates the device is not write enabled.
Bit 1 = “1” indicates the device is write enabled.
See
See
Instruction Format
3-1. All instructions, addresses, and data are transferred with the MSB first and start with a
Bit 5
Table
Table
X
0000 X110
0000 X100
0000 X101
0000 X001
0000 A011
0000 A010
3-4.
3-4.
Bit 4
X
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
Bit 3
BP1
AT25010B/020B/040B [Preliminary]
Bit 2
BP0
WEN
Bit 1
Bit 0
RDY
CC
is applied. All program-
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