25lc512 Microchip Technology Inc., 25lc512 Datasheet

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25lc512

Manufacturer Part Number
25lc512
Description
512 Kbit Spi Bus Serial Eeprom
Manufacturer
Microchip Technology Inc.
Datasheet

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Device Selection Table
Features:
• 20 MHz max. Clock Speed
• Byte and Page-level Write Operations
• Low-Power CMOS Technology
• Electronic Signature for Device ID
• Self-Timed Erase and Write cycles
• Sector Write Protection (16K byte/sector)
• Built-In Write Protection
• High Reliability
• Temperature Ranges Supported;
• Pb-free and RoHS Compliant
Pin Function Table
© 2007 Microchip Technology Inc.
CS
SO
WP
V
SI
SCK
HOLD
V
- 128-byte page
- 5 ms max.
- No page or sector erase required
- Max. Write Current: 5 mA at 5.5V, 20 MHz
- Read Current: 10 mA at 5.5V, 20 MHz
- Standby Current: 1μA at 2.5V (Deep power-
- Page Erase (5 ms, typical)
- Sector Erase (10 ms/sector, typical)
- Bulk Erase (10 ms, typical)
- Protect none, 1/4, 1/2 or all of array
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
- Endurance: 1 Million erase/write cycles
- Data Retention: >200 years
- ESD Protection: 4000V
- Industrial (I): -40°C to +85°C
SS
CC
Part Number
down)
Name
25AA512
Chip Select Input
Serial Data Output
Write-Protect
Ground
Serial Data Input
Serial Clock Input
Hold Input
Supply Voltage
512 Kbit SPI Bus Serial EEPROM
V
CC
1.8-5.5V
Function
Range
Page Size
128 Byte
Preliminary
Description:
The Microchip Technology Inc. 25AA512 is a 512 Kbit
serial EEPROM memory with byte-level and page-level
serial EEPROM functions. It also features Page, Sector
and Chip erase functions typically associated with
Flash-based products. These functions are not required
for byte or page write operations. The memory is
accessed via a simple Serial Peripheral Interface (SPI)
compatible serial bus. The bus signals required are a
clock input (SCK) plus separate data in (SI) and data out
(SO) lines. Access to the device is controlled by a Chip
Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts.
The 25AA512 is available in standard packages includ-
ing 8-lead PDIP, SOIC, and advanced 8-lead DFN
package. All packages are Pb-free and RoHS
compliant.
Package Types (not to scale)
V
WP
SO
CS
SS
Temp. Ranges
1
2
3
4
I
DFN
(MF)
8
7
6
5
25AA512
V
HOLD
SCK
SI
CC
P, SN, SM, MF
V
WP
SO
CS
SS
Packages
PDIP/SOIC/SOIJ
1
2
3
4
(P, SN, SM)
DS22021C-page 1
8
7
6
5
V
HOLD
SCK
SI
CC

Related parts for 25lc512

25lc512 Summary of contents

Page 1

... Temp. Ranges 128 Byte I Description: The Microchip Technology Inc. 25AA512 is a 512 Kbit serial EEPROM memory with byte-level and page-level serial EEPROM functions. It also features Page, Sector and Chip erase functions typically associated with Flash-based products. These functions are not required for byte or page write operations ...

Page 2

... V = 1. 2.0V to 5.5V CC Test Conditions ≥ 2.7V < 2. 1.0 mA, V < 2. -400 μ OUT 5.0V (Note) = 5.5V 20.0 MHz; CLK = 2.5V 10.0 MHz; CLK = 5.5V = 2.5V = 5.5V, Inputs tied 85°C = 2.5V, Inputs tied 85°C © 2007 Microchip Technology Inc. ...

Page 3

... This parameter is not tested but established by characterization and qualification. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. 3: Includes T time. HI © 2007 Microchip Technology Inc. Industrial (I)*: T = 0°C to +85°C A Industrial (I -40° ...

Page 4

... CC ≤ 5.5 CC < 5.5 CC <2.5 at 0°C to +85°C CC <2.5 at -40°C to +85°C CC ≤ 5.5 CC < 5.5 CC <2.5 at 0°C to +85°C CC <2.5 at -40°C to +85°C CC ≤ 5.5 CC < 5.5 CC <2.5 at 0°C to +85°C CC <2.5 at -40°C to +85° 1.8V to 5.5V = 1.8V to 5.5V = 1.8V to 5.5V = 1.8V to 5.5V © 2007 Microchip Technology Inc. ...

Page 5

... SCK 18 High-Impedance Don’t Care HOLD FIGURE 1-2: SERIAL INPUT TIMING CS 2 Mode 1,1 Mode 0,0 SCK MSB in SO © 2007 Microchip Technology Inc. — (Note 1) (Note 2) — High-Impedance Preliminary ...

Page 6

... FIGURE 1-3: SERIAL OUTPUT TIMING SCK 13 MSB out SO SI DS22021C-page 6 14 Don’t Care Preliminary 3 Mode 1,1 Mode 0,0 15 LSB out © 2007 Microchip Technology Inc. ...

Page 7

... WRDI 0000 0100 RDSR 0000 0101 WRSR 0000 0001 PE 0100 0010 SE 1101 1000 CE 1100 0111 RDID 1010 1011 DPD 1011 1001 © 2007 Microchip Technology Inc. BLOCK DIAGRAM STATUS Register ® Memory I/O Control Control Logic Logic SCK HOLD WP V ...

Page 8

... CS pin (Figure 2-1 16-bit Address Preliminary The instruction is READ Data Out © 2007 Microchip Technology Inc. ...

Page 9

... SI High-Impedance SO © 2007 Microchip Technology Inc. . Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘ ...

Page 10

... Address Data Byte Preliminary Data Byte Data Byte n (128 max © 2007 Microchip Technology Inc. ...

Page 11

... SI SO FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI) CS SCK SI SO © 2007 Microchip Technology Inc. • Power-up • WRDI instruction successfully executed • WRSR instruction successfully executed See • WRITE instruction successfully executed • PE instruction successfully executed • SE instruction successfully executed • CE instruction successfully executed ...

Page 12

... R R bits are nonvolatile, and are shown in Table 2-3. WEL WIP See Figure 2-6 for the RDSR timing sequence. 0 ’, no write Data from STATUS Register Preliminary © 2007 Microchip Technology Inc. ...

Page 13

... SI SO © 2007 Microchip Technology Inc. The Write-Protect Enable (WPEN) bit is a nonvolatile bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the STATUS register control the programmable hardware write-protect feature. Hard- ware write protection is enabled when WP pin is low and the WPEN bit is high ...

Page 14

... The write enable latch is reset • high-impedance state • A high-to-low-level transition required to enter active state Protected Blocks Unprotected Blocks Protected x Protected x Protected Protected Preliminary STATUS Register Protected Protected Writable Writable Writable Protected Writable Writable © 2007 Microchip Technology Inc. ...

Page 15

... SO © 2007 Microchip Technology Inc. CS must then be driven high after the last bit of the address or the PAGE ERASE will not execute. Once the CS is driven high the self-timed PAGE cycle is started. The WIP bit in the STATUS register can be read to determine when the PAGE ERASE cycle is complete ...

Page 16

... Block Protect bits (BP0, BP1) then the sequence will be aborted and no erase will occur. See Table 2-3 for Sector Addressing 16-bit Address High-Impedance Preliminary © 2007 Microchip Technology Inc. ...

Page 17

... CHIP ERASE SEQUENCE CS SCK SI SO © 2007 Microchip Technology Inc. The CS pin must be driven high after the eighth bit of the instruction code has been given or the CHIP ERASE instruction will not be executed. Once the CS pin is driven high the self-timed CHIP ERASE instruc- tion begins ...

Page 18

... Standby mode 16-bit Address Preliminary ) REL Electronic Signature Out Manufacturer’ 0x29 © 2007 Microchip Technology Inc. ...

Page 19

... SO © 2007 Microchip Technology Inc. Release from Deep Power-Down mode and Read Electronic Signature is entered by driving CS low, followed by the RDID instruction code (Figure 2-12) and then a dummy address of 16 bits (A15-A0). After the last bit of the dummy address is clock in, the 8-bit Electronic Signature is clocked out on the SO pin ...

Page 20

... SCK high-to-low transition. The SO line will tri-state immediately upon a high-to- low transition of the HOLD pin, and will begin outputting again immediately upon a subsequent low-to-high transition of the HOLD pin, independent of the state of SCK. Preliminary © 2007 Microchip Technology Inc. ...

Page 21

... Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. © 2007 Microchip Technology Inc. : Example 25AA512 ...

Page 22

... D N NOTE TOP VIEW A3 DS22021C-page EXPOSED PAD BOTTOM VIEW A A1 NOTE 2 Preliminary NOTE © 2007 Microchip Technology Inc. ...

Page 23

... N NOTE © 2007 Microchip Technology Inc Preliminary 25AA512 c DS22021C-page 23 ...

Page 24

... N NOTE DS22021C-page φ Preliminary α c β © 2007 Microchip Technology Inc. ...

Page 25

... Microchip Technology Inc. Preliminary 25AA512 DS22021C-page 25 ...

Page 26

... α DS22021C-page β Preliminary φ L © 2007 Microchip Technology Inc. ...

Page 27

... Revised Table 1-1 DC Characteristics; Revised Table 1-2 AC Characteristics; Replaced Pack- age Drawings (Rev. AP); Revised Package Marking (SOIC, SOIJ); Revised Product ID section. Revision C (10/2007) Removed 25LC512 part number; New data sheet created for 25LC512 (DS22065); Revised Tables; Updates throughout. © 2007 Microchip Technology Inc. Preliminary ...

Page 28

... NOTES: DS22021C-page 28 Preliminary © 2007 Microchip Technology Inc. ...

Page 29

... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2007 Microchip Technology Inc. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • ...

Page 30

... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS22021C-page 28 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS22021C Preliminary © 2007 Microchip Technology Inc. ...

Page 31

... Range: Package Micro Lead Frame ( body), 8-lead P = Plastic DIP (300 mil body), 8-lead SN = Plastic SOIC (3.90 mm body), 8-lead © 2007 Microchip Technology Inc. X /XX Examples: a) Package b) c) Preliminary 25AA512 . 25AA512-I/SN = 512 Kbit, 1.8V Serial EEPROM, Industrial temp., SOIC package 25AA512T-I/SM = 512 Kbit, 1.8V Serial EEPROM, Industrial temp., Tape & ...

Page 32

... NOTES: DS22021C-page 30 Preliminary © 2007 Microchip Technology Inc. ...

Page 33

... Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. © 2007 Microchip Technology Inc. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K ...

Page 34

... Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Preliminary © 2007 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris ...

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