at2450 Arrive Technologies, Inc., at2450 Datasheet - Page 5

• Manufacturer Part Number: at2450
• Description: Deep Channelization Multi-protocol Processor
• Manufacturer: Arrive Technologies, Inc.

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© 2007 Arrive Technologies All Rights Reserved
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including
LOF (red), AIS (blue), RAI (yellow)
AT&T 54016 FDL mode
(Near-End And Far-End), LOMF (Loss Of Multi-Frame)
G.704
including
LOF, AIS, RAI (Remote Alarm Indication)
bit to 32-bit
Up to 672 DS1 framers
Supports SF/ESF/SLC-96/DDS framing
Supports J1 SF/ESF framing
Independent Clocking modes for each transmit DS1
Loopback capabilities:
Supports loopback detection/insertion
Error and alarm detection: CRC errors, framing errors,
BERT generator and detector at DS1 level including
ANSI T1.403 facility data link (FDL) on ESF mode and
Local and remote performance monitoring (PM)
Detect and insert BOC (Bit Oriented Commands)
Alarm and event detection: AIS, RDI, LOS and LOF
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Up to 504 E1 framers
Framing: CRC-4 and non-CRC-4 conformance with ITU-T
Independent Clocking modes for each transmit E1
Loopback capabilities:
Error and alarm detection: CRC errors, framing errors,
BERT generator and detector at E1 level including
A configurable fixed pattern which is selectable from 1-
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DS1 with F-bit overwrite
DDS1/2/3/4/5, Fix 3 in 28, Fix 1 in 8, DALY/55
Octet
from 1-bit to 32-bit
DDS1/2/3/4/5, Fix 3 in 28, Fix 1 in 8, DALY/55
Octet
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Derived from corresponding receive DS1
Derived from any of SONET/SDH lines
Internal generation by the Europa system clock
Remote line loopback
Remote payload loopback
Local line loopback
Local payload loopback
Inband loopcode on DS1 payload, full DS1 or
FDL channel
QRSS, PRBS 9/11/15/20/23 (inverted or not),
A configurable fixed pattern which is selectable
Derived from corresponding receive E1
Derived from any of SONET/SDH lines
Internal generation by the Europa system clock
Remote line loopback
Remote payload loopback
Local line loopback
Local payload loopback
QRSS, PRBS 9/11/15/20/23 (inverted or not),
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Deep Channelization Multi-Protocol Processor
Rev. 2.0 – July 2008
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for 2048 data channels
compliance with G.8040, X.85/86, G.804 and IEEE 802.6
DS1, E1, DS3, E3 and NxDS0
with the assistance of an external Network Processor
to-Point Protocol (ML PPP) with the assistance of an
external Network Processor
RFC-1619/1662/2615 (PPP), ITU-T X.85/86 (LAPS), HDLC
mapping standards
DS1/E1/DS3/E3 through the SPI interface
error correction
generation
per channel data
and checking for GFP and FCS Ethernet/PPP
Up to 16128 DS0s
Signaling processor for ABCD signaling scan
Signaling de-bounce
Signaling freeze and signaling conversion
ATM, GFP, PPP/HDLC, LAPS simultaneously, full-duplex
GFP/HDLC/PPP/BCP/LAPS/ATM mapping to PDH in
Supports direct ATM cell mapping for STS/VC, VT/TU,
Supports ATM direct mapping or PLCP for 24xDS3/E3
Supports Cisco HDLC
Supports Frame Relay mapping
Supports Inverse Multiplexing over ATM (IMA) across PDH
Supports Multilink Frame Relay (ML FR), Multilink Point-
Complies with ITU-T I432.2 (ATM), ITU-T G.7041 (GFP),
Supports transparent mode to pass STS/VC, VT/VC,
Cell HEC and packet FCS checker/generator and 1-bit HEC
Idle/unassigned cell and aborted sequence detection/
Cell/packet payload scrambling/de-scrambling
Supports 16 or 32 bit frame check sequence field (FCS)
Supports GFP-F with double configuration FCS generation
Supports ATM idle cell discard or pass-through
Bit stuffing and byte stuffing on PPP and HDLC
Extraction and insertion header field support
Supports frame extraction and insertion
Various statistic events per GFP data channel
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Good frame counters on transmit and receive
cHEC, tHEC, eHEC uncorrected error counters
FCS error counters
Frame drop/discard event counters
Idle frame counter on receive
Transmit underrun counter
Transmit unexpected length error counter
Out of frame delineation event
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AT2450 Preliminary Short Data Sheet
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VIETNAM
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