at24c02c ATMEL Corporation, at24c02c Datasheet - Page 6

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at24c02c

Manufacturer Part Number
at24c02c
Description
Two-wire Serial Eeprom 2k 256 X 8
Manufacturer
ATMEL Corporation
Datasheet

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3. Device Operation
Figure 3-1.
6
SCL
SDA
AT24C02C [Preliminary]
Software reset
Start bit
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device.
Data on the SDA pin may change only during SCL low time periods (see
Data changes during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see
ure 5-3 on page
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each
word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C02C features a low-power standby mode which is enabled: (a)
upon power-up and (b) after the receipt of the STOP bit and the completion of any internal
operations.
2-Wire Software Reset: After an interruption in protocol, power loss or system reset, any 2-wire
part can be reset by following these steps: (a) Create a start bit condition, (b) clock 9 cycles, (c)
create another start bit followed by stop bit condition as shown below. The device is ready for
next communication after above steps have been completed.
1
8).
2
Dummy Clock Cycles
3
Figure 5-3 on page
8
9
8).
Start bit
Figure 5-2 on page
8700B–DEEPR–2/10
Stop b
Fig-
8).

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