nlsf1174 ON Semiconductor, nlsf1174 Datasheet

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nlsf1174

Manufacturer Part Number
nlsf1174
Description
Hex D Flipflop With Common Clock And Reset
Manufacturer
ON Semiconductor
Datasheet
NLSF1174
Hex D Flip−Flop with
Common Clock and Reset
Reset inputs. Each flip−flop is loaded with a low−to−high transition of
the Clock input. Reset is asynchronous and active low. All
inputs/outputs are standard CMOS compatible.
Features
*For additional information on our Pb−Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2006
May, 2006 − Rev. 5
Q1
D0
D1
D2
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
This device consists of six D flip−flops with common Clock and
Output Drive Compatibility: 10 LSTTL Loads
Outputs Directly Interface to CMOS
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
MSL Level 1
Chip Complexity: 162 FET
Pb−Free Package is Available*
Center pad on bottom may be connected to V
This pad must be isolated or connected to V
1
2
3
4
Figure 1. PIN ASSIGNMENT (Top View)
Q0
Q2
16
5
Reset
GND
15
6
Clock
V
14
7
CC
CC
Q5
Q3
CC
13
8
.
of device.
12
10
11
9
D5
D4
Q4
D3
1
†For information on tape and reel specifications,
NLSF1174MNR2
NLSF1174MNR2G
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Reset
(Note: Microdot may be in either location)
H
H
H
H
L
Device
NLSF1174 = Device Code
A
L
Y
W
G
ORDERING INFORMATION
1
MARKING DIAGRAM
Ç Ç Ç
Ç Ç Ç
FUNCTION TABLE
http://onsemi.com
1
Inputs
Clock
16
X
L
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Pb−Free)
Package
QFN−16
QFN−16
ALYW G
NLSF
1174
Publication Order Number:
G
MN SUFFIX
CASE 485G
QFN−16
3000 / Tape & Reel
3000 / Tape & Reel
D
X
H
X
X
L
Shipping
NLSF1174/D
No Change
No Change
Output
Q
H
L
L

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nlsf1174 Summary of contents

Page 1

... QFN−16 MN SUFFIX CASE 485G 1 MARKING DIAGRAM 16 Ç Ç Ç 1 Ç Ç Ç NLSF 1174 ALYW G G NLSF1174 = Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) FUNCTION TABLE Inputs ...

Page 2

... I absolute maximum rating must be observed Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78. 6. For high frequency or heavy load considerations, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D). NLSF1174 RESET Figure 2 ...

Page 3

... For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D). 10. Used to determine the no−load dynamic power consumption: P Semiconductor High−Speed CMOS Data Book (DL129/D). NLSF1174 Parameter (Referenced to GND) (Referenced to GND) (Note ...

Page 4

... Maximum Input Rise and Fall Times Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î CLOCK RESET NLSF1174 = t = 6.0 ns ...

Page 5

... Q 50% 10 TLH THL Figure 4. Switching Waveform VALID DATA 50 CLOCK 50% Figure 6. Switching Waveform PIN1/PRODUCT ORIENTATION CARRIER TAPE NLSF1174 V CC RESET GND t PHL Q CLOCK Figure 5. Switching Waveform V CC DEVICE UNDER GND TEST V CC GND *Includes all probe and jig capacitance Figure 7 ...

Page 6

... CONDITION CAN NOT VIOLATE 0.2 MM max MINIMUM SPACING BETWEEN LEAD TIP AND FLAG MILLIMETERS DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF b 0.18 0.30 D 3.00 BSC D2 1.65 1.85 E 3.00 BSC E2 1.65 1.85 e 0.50 BSC K 0.18 TYP L 0.30 0.50 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NLSF1174/D ...

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