DS1921H/Z Maxim Integrated Products, DS1921H/Z Datasheet - Page 30

• Manufacturer Part Number: DS1921H/Z
• Description: High Resolution Thermochron Ibutton Range H
• Manufacturer: Maxim Integrated Products

DS1921H/Z
The master samples the data line at t
, inside a window that is determined by the sum of t
and the rise
MSR
RL
time (d) on one side and t
on the other side. The optimum sample point for a read-zero case is no
SPDMIN
later than t
. In case of a read-one, the voltage on the 1-Wire line must be able to reach V
at
SPDMIN
IHMASTER
t
. This condition determines the maximum duration of the master pull-down time. For reliable
MSR
communication, the master pull-down time should be as short as possible, maximizing the time for the
data line to reach V
. Before the next time slot can start, t
needs to be over and the voltage on
IHMIN
SPDMAX
the data line must have risen above V
and remained there until the recovery time t
is expired.
TH
REC
CRC GENERATION
With the DS1921H/Z there are two different types of Cyclic Redundancy Checks (CRCs). One CRC is an
8-bit type and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a
CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the
DS1921H/Z to determine if the ROM data has been received error-free. The equivalent polynomial
8
5
4
function of this CRC is X
+ X
+ X
+ 1. This 8-bit CRC is received in the true (noninverted) form. It is
computed at the factory and lasered into the ROM.
16
The other CRC is a 16-bit type, generated according to the standardized CRC16-polynomial function X
15
2
+ X
+ X
+ 1. This CRC is used for error detection when reading data memory using the Read Memory
with CRC command and for fast verification of a data transfer when writing to or reading from the
scratchpad. It is the same type of CRC as is used with NV RAM-based iButtons for error detection within
the iButton Extended File Structure. In contrast to the 8-bit CRC, the 16-bit CRC is always communi-
cated in the inverted form. A CRC-generator inside the DS1921H/Z chip (Figure 15) will calculate a new
16-bit CRC as shown in the command flow chart of Figure 10. The bus master compares the CRC value
read from the device to the one it calculates from the data and decides whether to continue with an opera-
tion or to reread the portion of the data with the CRC error. With the initial pass through the Read Mem-
ory with CRC flow chart, the 16-bit CRC value is the result of shifting the command byte into the cleared
CRC generator, followed by the 2 address bytes and the data bytes. Subsequent passes through the Read
Memory with CRC flow chart will generate a 16-bit CRC that is the result of clearing the CRC generator
and then shifting in the data bytes
.
With the Write Scratchpad command the CRC is generated by first clearing the CRC generator and then
shifting in the command code, the Target Addresses TA1 and TA2 and all the data bytes. The
DS1921H/Z will transmit this CRC only if the data bytes written to the scratchpad include scratchpad
ending offset 11111b. The data may start at any location within the scratchpad.
With the Read Scratchpad command the CRC is generated by first clearing the CRC generator and then
shifting in the command code, the target addresses (TA1 and TA2), the E/S byte, and the scratchpad data
starting at the target address. The DS1921H/Z will transmit this CRC only if the reading continues
through the end of the scratchpad, regardless of the actual ending offset.
For more information on generating CRC values see Application Note 27 or the Book of DS19xx iButton
Standards.
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