74ACT823SC Fairchild Semiconductor, 74ACT823SC Datasheet - Page 2

• Manufacturer Part Number: 74ACT823SC
• Description: IC FLIP FLOP D-TYPE 9-BIT 24SOIC
• Manufacturer: Fairchild Semiconductor
• Series: 74ACTr
• Type: D-Type Busr

Specifications of 74ACT823SC

• Function: Master Reset
• Output Type: Tri-State Non Inverted
• Number Of Elements: 1
• Number Of Bits Per Element: 9
• Frequency - Clock: 158MHz
• Delay Time - Propagation: 5.5ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Functional Description
The ACT823 consists of nine D-type edge-triggered flip-
flops. These have 3-STATE outputs for bus systems orga-
nized with inputs and outputs on opposite sides. The buff-
ered clock (CP) and buffered Output Enable (OE) are
common to all flip-flops. The flip-flops will store the state of
their individual D-type inputs that meet the setup and hold
time requirements on the LOW-to-HIGH CP transition. With
OE LOW, the contents of the flip-flops are available at the
outputs. When OE is HIGH, the outputs go to the high
impedance state. Operation of the OE input does not affect
the state of the flip-flops. In addition to the Clock and Out-
Function Table
H
L
X

Z
NC
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
LOW Voltage Level
High Impedance
HIGH Voltage Level
Immaterial
LOW-to-HIGH Transition
No Change
OE
H
H
H
H
H
H
L
L
L
L
CLR
H
H
H
H
H
H
X
X
L
L
Inputs
EN
H
H
L
L
X
X
L
L
L
L
CP






X
X
X
X
D
H
X
X
X
X
H
H
L
L
L
2
Internal
put Enable pins, there are Clear (CLR) and Clock Enable
(EN) pins. These devices are ideal for parity bus interfacing
in high performance systems.
When CLR is LOW and OE is LOW, the outputs are LOW.
When CLR is HIGH, data can be entered into the flip-flops.
When EN is LOW, data on the inputs is transferred to the
outputs on the LOW-to-HIGH clock transition. When the
EN is HIGH, the outputs do not change state, regardless of
the data or clock input transitions.
NC
NC
Q
H
H
H
L
L
L
L
L
Output
NC
O
H
Z
Z
Z
L
Z
Z
Z
L
High Z
High Z
Clear
Clear
Hold
Hold
Load
Load
Load
Load
Function