74alvt16601 NXP Semiconductors, 74alvt16601 Datasheet

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74alvt16601

Manufacturer Part Number
74alvt16601
Description
18-bit Universal Bus Transceiver 3-state
Manufacturer
NXP Semiconductors
Datasheet

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Part Number:
74alvt16601DGG
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
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Part Number:
74alvt16601DGG
Quantity:
2 000
1. General description
2. Features
The 74ALVT16601 is a high-performance Bipolar Complementary Metal Oxide
Semiconductor (BiCMOS) product designed for V
compatibility up to 5 V. This device is an 18-bit universal transceiver featuring
non-inverting 3-state bus compatible outputs in both send and receive directions. Data
flow in each direction is controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device
operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A-bus
data is latched if CPAB is held at a HIGH or LOW level. If LEAB is LOW, the A-bus data is
stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is LOW,
the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state.
The clocks can be controlled with the clock enable inputs (CEAB and CEBA).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
74ALVT16601
18-bit universal bus transceiver; 3-state
Rev. 03 — 5 July 2005
18-bit bidirectional bus interface
5 V I/O compatible
3-state buffers
Output capability: +64 mA and 32 mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
Live insertion and extraction permitted
Power-up reset
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Positive-edge triggered clock inputs
Latch-up protection:
ESD protection:
JESD78: exceeds 500 mA
MIL STD 883, method 3015: exceeds 2000 V
Machine model: exceeds 200 V
CC
operation at 2.5 V and 3.3 V with I/O
Product data sheet

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74alvt16601 Summary of contents

Page 1

... Rev. 03 — 5 July 2005 1. General description The 74ALVT16601 is a high-performance Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) product designed for V compatibility This device is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data fl ...

Page 2

... I/O pins supply current Name Description SSOP56 plastic shrink small outline package; 56 leads; body width 7.5 mm TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm Rev. 03 — 5 July 2005 74ALVT16601 18-bit universal bus transceiver; 3-state Conditions Min Typ 1 ...

Page 3

... B10 40 B11 38 B12 37 B13 36 B14 34 B15 33 B16 31 B17 27 OEBA LEBA CPBA CEBA 001aad316 Fig 2. IEC logic symbol Rev. 03 — 5 July 2005 74ALVT16601 18-bit universal bus transceiver; 3-state 1 EN1 OEAB 56 CEAB G2 55 CPAB 2C3 2 LEAB EN4 OEBA 29 G5 CEBA 30 CPBA 5C6 ...

Page 4

... Product data sheet 1 OEAB 56 CEAB 55 CPAB 2 LEAB 28 LEBA 30 CPBA 29 CEBA 27 OEBA CLK to 17 other channels Rev. 03 — 5 July 2005 74ALVT16601 18-bit universal bus transceiver; 3-state CLK 001aad249 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...

Page 5

... A-to-B output enable input (active LOW) 2 A-to-B latch enable input 3 data input or output (A side) 4 ground ( data input or output (A side) 6 data input or output (A side) 7 voltage supply 8 data input or output (A side) Rev. 03 — 5 July 2005 74ALVT16601 18-bit universal bus transceiver; 3-state 56 CEAB 55 CPAB GND ...

Page 6

... V) 47 data input or output (B side) 48 data input or output (B side) 49 data input or output (B side) Rev. 03 — 5 July 2005 74ALVT16601 18-bit universal bus transceiver; 3-state © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...

Page 7

... LEAB OEBA LEBA Limiting values Conditions supply voltage input voltage output voltage output in OFF-state or HIGH-state Rev. 03 — 5 July 2005 74ALVT16601 18-bit universal bus transceiver; 3-state Input CPAB An CPBA Min ...

Page 8

... LOW-level input voltage HIGH-level output current LOW-level output current none current duty cycle kHz input transition rise or fall outputs enabled rate ambient temperature in free air Rev. 03 — 5 July 2005 74ALVT16601 18-bit universal bus transceiver; 3-state Min Max - 128 - 64 65 ...

Page 9

... V to 2.7 V; one input 0.6 V, other inputs GND outputs disabled 100 3 Rev. 03 — 5 July 2005 74ALVT16601 Min Typ Max - 0.85 1 0.2 1 0.07 0.2 - 0.3 0 0.4 [ 0.55 - 0.1 1 0 ...

Page 10

... V and 1.2 V with a transition time ms. From only. amb or pulled down to ground amb between 0 V and 1.2 V with a transition time ms. From only. amb Rev. 03 — 5 July 2005 74ALVT16601 18-bit universal bus transceiver; 3-state Min Typ - 0.07 - 0.25 - 0.3 - ...

Page 11

... Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 7 see Figure 6 see Figure 7 Rev. 03 — 5 July 2005 74ALVT16601 Min Typ Max Unit 1.4 2.2 3.5 ns 1.5 2.5 4.0 ns 1.9 3.2 5.2 ns 1.0 1.8 3.0 ns 1.5 2.5 4.0 ns 2.2 3.5 5.0 ns 2.2 3 ...

Page 12

... Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 8 see Figure 7 see Figure 6 see Figure 7 = 2.5 V and amb = 3.3 V and amb Rev. 03 — 5 July 2005 74ALVT16601 18-bit universal bus transceiver; 3-state 11. Min Typ 1.1 2.0 1.4 2.3 1.7 2.7 1.2 1.9 1.5 2.5 2.1 3.1 2.7 3.6 2.1 2.8 2.2 3.2 1.6 2.5 +1.0 0.5 1.5 0.1 1 ...

Page 13

... V OL Measurement points are given in Table V and V are typical voltage output drop that occur with the output load (CPAB, CPBA) and maximum clock frequency (CPAB, CPBA) Rev. 03 — 5 July 2005 74ALVT16601 18-bit universal bus transceiver; 3-state PLH PHL V V ...

Page 14

... V I input OEBA or OEAB output Measurement points are given in Table V is typical voltage output drop that occur with the output load. OL Rev. 03 — 5 July 2005 74ALVT16601 18-bit universal bus transceiver; 3-state h(H) su(L) h( ...

Page 15

... Termination resistance should be equal to output impedance Test voltage for switching times. EXT Test data MHz 500 ns 2 Rev. 03 — 5 July 2005 74ALVT16601 18-bit universal bus transceiver; 3-state 0 0. ...

Page 16

... scale (1) ( 0.3 0.22 18.55 7.6 10.4 0.635 0.2 0.13 18.30 7.4 10.1 REFERENCES JEDEC JEITA MO-118 Rev. 03 — 5 July 2005 74ALVT16601 18-bit universal bus transceiver; 3-state detail 1.0 1.2 1.4 0.25 0.18 0.1 0.6 1.0 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...

Page 17

... Product data sheet 2.5 scale (1) ( 0.28 0.2 0.2 14.1 6.2 0.5 0.17 0.1 0.1 13.9 6.0 REFERENCES JEDEC JEITA MO-153 Rev. 03 — 5 July 2005 74ALVT16601 18-bit universal bus transceiver; 3-state detail 8.3 0.8 0.50 1 0.25 0.08 7.9 0.4 0.35 EUROPEAN PROJECTION © ...

Page 18

... Std 17’ into ‘JESD78’. characteristics”: changed values of propagation delay, output enable and Product specification - - - Rev. 03 — 5 July 2005 74ALVT16601 18-bit universal bus transceiver; 3-state Doc. number Supersedes - 74ALVT16601_2 9397 750 03571 74ALVT16601_1 - - © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...

Page 19

... Trademarks Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. Rev. 03 — 5 July 2005 74ALVT16601 18-bit universal bus transceiver; 3-state © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...

Page 20

... No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Published in The Netherlands Date of release: 5 July 2005 Document number: 74ALVT16601_3 ...

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