74alvc574 NXP Semiconductors, 74alvc574 Datasheet

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74alvc574

Manufacturer Part Number
74alvc574
Description
Octal D-type Flip-flop Positive Edge-trigger 3-state
Manufacturer
NXP Semiconductors
Datasheet

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74alvc574PW
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1. General description
2. Features
The 74ALVC574 is an octal D-type flip-flop featuring separate D-type inputs for each
flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an
outputs enable input (OE) are common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs that meet the set-up and
hold times requirements on the LOW to HIGH CP transition.
When pin OE is LOW, the contents of the eight flip-flops is available at the outputs. When
pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the flip-flops.
The 74ALVC574 is functionally identical to the 74ALVC374, but has a different pin
arrangement.
74ALVC574
Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 02 — 8 November 2007
Wide supply voltage range from 1.65 V to 3.6 V
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
Complies with JEDEC standards:
ESD protection:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115A exceeds 200 V
Product data sheet

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74alvc574 Summary of contents

Page 1

... When pin OE is LOW, the contents of the eight flip-flops is available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The 74ALVC574 is functionally identical to the 74ALVC374, but has a different pin arrangement. 2. Features Wide supply voltage range from 1 ...

Page 2

... mna798 Fig 2. IEC logic symbol FF1 3-STATE OUTPUTS FF8 Rev. 02 — 8 November 2007 74ALVC574 0. mna446 ...

Page 3

... Fig 4. Logic diagram 74ALVC574_2 Product data sheet Octal D-type flip-flop; positive edge-trigger; 3-state FF3 FF4 Rev. 02 — 8 November 2007 74ALVC574 FF5 FF6 FF7 Q4 Q5 © NXP B.V. 2007. All rights reserved ...

Page 4

... Fig 6. Pin configuration DHVQFN20 Description data input clock input (LOW to HIGH, edge-triggered) output enable input (active LOW) 3-state flip-flop output supply voltage ground (0 V) Rev. 02 — 8 November 2007 74ALVC574 74ALVC574 terminal 1 index area ...

Page 5

... > < output HIGH or LOW state output 3-state power-down mode +85 C amb Rev. 02 — 8 November 2007 74ALVC574 Internal flip-flop Output Min Max Unit 0.5 +4 0.5 +4.6 ...

Page 6

... GND CC I Rev. 02 — 8 November 2007 74ALVC574 Min Max 1.65 3 3 +85 C [1] Min Typ 0. 1 ...

Page 7

... Figure clock HIGH or LOW; see Figure Rev. 02 — 8 November 2007 74ALVC574 +85 C [1] Min Typ - 0.1 - 0 amb 10 +85 C [1] Min Typ [2] 1.0 3.1 1.0 2.3 1.0 2 ...

Page 8

... per flip-flop GND outputs HIGH or LOW state outputs 3-state = 25 C amb in W where Rev. 02 — 8 November 2007 74ALVC574 Figure 10 +85 C Min Typ 0.8 0.1 0.8 0.1 0.8 0.3 0.8 0.0 0.8 0.1 0.8 0.1 0.8 0.4 0.7 0.1 100 200 100 200 150 ...

Page 9

... V M 0.5V CC 0.5V CC 1 GND t PLZ PHZ GND outputs outputs enabled disabled Table 8. Rev. 02 — 8 November 2007 74ALVC574 t PLH mna894 PZL V ...

Page 10

... Fig 9. Data set-up and hold times for the Dn input to the CP input 74ALVC574_2 Product data sheet Octal D-type flip-flop; positive edge-trigger; 3-state GND GND Table 8. Rev. 02 — 8 November 2007 74ALVC574 mna202 © NXP B.V. 2007. All rights reserved ...

Page 11

... DUT R T Load Rev. 02 — 8 November 2007 74ALVC574 EXT 001aae331 of the pulse generator EXT PLH PHL ...

Page 12

... 0.49 0.32 13.0 7.6 10.65 1.27 0.36 0.23 12.6 7.4 10.00 0.019 0.013 0.51 0.30 0.419 0.05 0.014 0.009 0.49 0.29 0.394 REFERENCES JEDEC JEITA MS-013 Rev. 02 — 8 November 2007 74ALVC574 detail 1.1 1.1 1.4 0.25 0.25 0.4 1.0 0.043 0.043 0.055 0.01 0.01 0.016 0.039 EUROPEAN PROJECTION ...

Page 13

... Octal D-type flip-flop; positive edge-trigger; 3-state 2.5 scale (1) ( 0.30 0.2 6.6 4.5 0.65 0.19 0.1 6.4 4.3 REFERENCES JEDEC JEITA MO-153 Rev. 02 — 8 November 2007 74ALVC574 detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN ...

Page 14

... Octal D-type flip-flop; positive edge-trigger; 3-state 2.5 scale (1) ( 4.6 3.15 2.6 1.15 0.5 3.5 4.4 2.85 2.4 0.85 REFERENCES JEDEC JEITA MO-241 - - - Rev. 02 — 8 November 2007 74ALVC574 detail 0.5 0.05 0.1 0.1 0.05 0.3 EUROPEAN PROJECTION SOT764 ...

Page 15

... Octal D-type flip-flop; positive edge-trigger; 3-state Data sheet status Product data sheet 3: DHVQFN20 package added. 8: derating values added for DHVQFN20 package. 12: outline drawing added for DHVQFN20 package. Product specification Rev. 02 — 8 November 2007 74ALVC574 Change notice Supersedes - 74ALVC574_1 - - © NXP B.V. 2007. All rights reserved ...

Page 16

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 8 November 2007 74ALVC574 © NXP B.V. 2007. All rights reserved ...

Page 17

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74ALVC574 All rights reserved. Date of release: 8 November 2007 Document identifier: 74ALVC574_2 ...

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