74aup1g386gw NXP Semiconductors, 74aup1g386gw Datasheet

74aup1g386gw

Manufacturer Part Number

74aup1g386gw

Description

74aup1g386 Low-power 3-input Exclusive-or Gate

Manufacturer

NXP Semiconductors

Datasheet

1.74AUP1G386GW.pdf (16 pages)

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1. General description

2. Features

The 74AUP1G386 is a high-performance, low-power, low-voltage, Si-gate CMOS device,

superior to most advanced CMOS compatible TTL families.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V

This device ensures a very low static and dynamic power consumption across the entire

This device is fully speciﬁed for partial power-down applications using I

The I

the device when it is powered down.

The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate.

74AUP1G386

Low-power 3-input EXCLUSIVE-OR gate

Rev. 02 — 10 January 2008

Wide supply voltage range from 0.8 V to 3.6 V

High noise immunity

Complies with JEDEC standards:

ESD protection:

Low static power consumption; I

Latch-up performance exceeds 100 mA per JESD 78 Class II

Inputs accept voltages up to 3.6 V

Low noise overshoot and undershoot < 10 % of V

Multiple package options

Speciﬁed from 40 C to +85 C and 40 C to +125 C

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range from 0.8 V to 3.6 V.

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JESD8-12 (0.8 V to 1.3 V)

JESD8-11 (0.9 V to 1.65 V)

JESD8-7 (1.2 V to 1.95 V)

JESD8-5 (1.8 V to 2.7 V)

JESD8-B (2.7 V to 3.6 V)

HBM JESD22-A114E Class 3A exceeds 5000 V

MM JESD22-A115-A exceeds 200 V

CDM JESD22-C101-C exceeds 1000 V

circuitry provides partial Power-down mode operation

circuitry disables the output, preventing the damaging backﬂow current through

range from 0.8 V to 3.6 V.

= 0.9 A (maximum)

Product data sheet

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