dm74ls192 National Semiconductor Corporation, dm74ls192 Datasheet - Page 3

• Manufacturer Part Number: dm74ls192
• Description: 54ls192/dm74ls192 Up/down Decade Counter With Separate Up/down Clocks
• Manufacturer: National Semiconductor Corporation

Switching Characterisitcs
V
Functional Description
The ’192 is an asynchronously presettable decade and 4-bit
binary synchronous up down (reversible) counter The op-
erating modes of the ’192 decade counter and the ’193 bi-
nary counter are identical with the only difference being the
count sequences as noted in the State Diagram Each cir-
cuit contains four master slave flip-flops with internal gat-
ing and steering logic to provide master reset individual pre-
set count up and count down operations
Each flip-flop contains JK feedback from slave to master
such that a LOW-to-HIGH transition on its T input causes
the slave and thus the Q output to change state Synchro-
nous switching as opposed to ripple counting is achieved
by driving the steering gates of all stages from a common
Count Up line and a common Count Down line thereby
causing all state changes to be initiated simultaneously A
LOW-to-HIGH transition on the Count Up input will advance
the count by one a similar transition on the Count Down
input will decrease the count by one While counting with
one clock input the other should be held HIGH Otherwise
the circuit will either count by twos or not at all depending
on the state of the first flip-flop which cannot toggle as long
as either Clock input is LOW
The Terminal Count Up (TC
(TC
reached the maximum count state (9 for the ’192 15 for the
’193) the next HIGH-to-LOW transition of the Count Up
Clock will cause TC
CP
Up Clock but delayed by two gate delays Similarly the TC
output will go LOW when the circuit is in the zero state and
the Count Down Clock goes LOW Since the TC outputs
repeat the clock waveforms they can be used as the clock
input signals to the next higher order circuit in a multistage
counter
CC
U
D
e a
) outputs are normally HIGH When a circuit has
goes HIGH again thus effectively repeating the Count
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PHL
0 5V T
A
e a
U
to go LOW TC
25 C (See Section 1 for waveforms and load configurations)
U
Maximum Count Frequency
Propagation Delay
CP
Propagation Delay
CP
Propagation Delay
CP
Propagation Delay
P
Propagation Delay
PL to Q
Propagation Delay MR to Q
) and Terminal Count Down
n
U
U
D
to Q
or CP
to TC
to TC
n
n
U
Parameter
D
U
D
will stay LOW until
to Q
n
n
D
3
Each circuit has an asynchronous parallel load capability
permitting the counter to be reset When the Parallel Load
(PL) and the Master Reset (MR) inputs are LOW informa-
tion present on the Parallel Data inputs (P0 – P3) is loaded
into the counter and appears on the outputs regardless of
the conditions of the clock inputs A HIGH signal on the
Master Reset input will disable the preset gates override
both Clock inputs and latch each Q output in the LOW
state If one of the Clock inputs is LOW during and after a
reset or load operation the next LOW-to-HIGH transition of
that Clock will be interpreted as a legitimate signal and will
be counted
State Diagram
Min
30
TC
C
L
R
D
L
e
e
TC
e
15 pF
Q0
U
2k
e

Q0
Q1
Max
31
28
16
21
16
24
20
30
32
30
25


Q3
Q2


CP
Q3
U

CP
D
TL F 10178 – 4
Units
MHz
ns
ns
ns
ns