ml6461 Micro Electronics Corporation, ml6461 Datasheet - Page 13

• Manufacturer Part Number: ml6461
• Description: Ntsc Video Encoder
• Manufacturer: Micro Electronics Corporation

FUNCTIONAL DESCRIPTION
Internal Slave Mode
Embedded in the YCrCb data stream, the timing code
0xFF, 0x00, 0x00, 0x(SAV) must be inserted before the
samples of the first active pixel. Figures 6 through 6b
illustrate timing for CCIR656 video with SAV and EAV
codes for CCIR or Square Pixel clocking.
External Slave Mode
A horizontal reset pulse can be used either at the beginning
of active video or the beginning of horizontal blanking to
provide synchronization of the YCrCb data to the internal
clock. Bits SEL_HSYNC1(B14) and SEL_HSYNC0 (B13) are
provided to achieve some degree of programmability in this
synchronization. Figures 7 and 7a show synchronization for
active edge at the beginning of active video for positive or
negative HSYNC polarity while Figures 8 and 8a show
synchronization for active edge at the beginning of
horizontal blanking for positive or negative HSYNC polarity.
Polarity of HSYNC and VSYNC
In both the Master and Slave modes, the HSYNC and
VSYNC polarity can be selected via bit SENSE_HSYNC and
SENSE_VSYNC. When the SENSE_HSYNC bit is set to
logical 1, the HSYNC pulse is on the rising edge. When the
SENSE_HSYNC bit is cleared to logical 0, the HSYNC pulse
is on the falling edge. Similarly, when the SENSE_VSYNC bit
is set logical 1, the VSYNC pulse is on the rising edge.
CB0
In CCIR format, there are
0 1 2 3 4 5 6 7
F
F
0
0
4
0
0
Y0
A
V
E
CR0
8
0
1
0
8
0
BLANKING
Y1
1
0
CB1
{ }
ACTIVE
360 Cb
360 Cr
720 Y
Y2
• • • • • • •
CR1
268
in the active portion of a line.
Y3
Figure 6. CCIR Format: CLK = 27MHz
(Continued)
CB2 Y4
270
8
0
1
0
1440
272
F
F
• • • • • • •
0
0
4
274
0
0
When the SENSE_VSYNC bit is cleared to logical 0, the
VSYNC pulse is on the falling edge.
HSYNC Timing Delay
and SEL_HSYNC0 (B13) bits of the control register can be
programmed to delay the HSYNC active edge up to three
clock periods, 3T, where T is one period of the clock.
CHROMA AND LUMA PROCESSING
Refer to Figures 9 through 12.
VIDEO OUTPUT STAGE
Reconstruction filtering, clamping, and line drivers
The ML6461 can simultaneously provide outputs for S-
video, two composite video, and a TV modulator.
Differential gain and phase are guaranteed at the outputs
of the line drivers. Two internal 7
filters and a group delay equalizer are used as
reconstruction filters on S-video (NTSC). The composite
signal is generated after reconstruction. The S-video (Y and
C) and composite video (CV) are then fed into 75
drivers.
Each of the filter/drivers are designed to guarantee a
differential phase of 0.5º and differential gain of 0.5%.
A
V
S
In both Master and Slave modes, the SEL_HSYNC1(B14)
276
C
B
Y C
278
R
Y715 CB358 Y716 CR358 Y717 CB359 Y718 CR359 Y719
Y C
ACTIVE
280
B
Y C
282
R
Y
LINE
1440
• • • • • • •
LINE
th
-order Butterworth
1711
Y C
B
1713
Y C
R
1715
ML6461
Y
line
13