adcmp553 Analog Devices, Inc., adcmp553 Datasheet - Page 6

• Manufacturer Part Number: adcmp553
• Description: Single Supply High Speed Pecl Comparators
• Manufacturer: Analog Devices, Inc.

ADCMP551/ADCMP552/ADCMP553
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
ADCMP551
3, 14
1
2
4
5
6
7
8
9
10
11
V
Figure 2. ADCMP551 16-Lead QSOP
–INA
+INA
V
LEA
LEA
CCO
QA
QA
CCI
1
2
3
4
5
6
7
8
Pin Configuration
ADCMP552
1, 4, 17, 20
2
3
5
6
7
8
9
10
11
12
13
14
ADCMP551
(Not to Scale)
TOP VIEW
Pin No.
16
15
14
13
12
11
10
9
ADCMP553
6
5
2
1
4
3
8
QB
QB
V
LEB
LEB
AGND
–INB
+INB
CCO
HYSA
HYSB
+INB
−INB
AGND
Mnemonic
V
QA
QA
LEA
LEA
V
−INA
+INA
CCO
CCI
HYSA
V
V
Figure 3. ADCMP552 20-Lead QSOP
–INA
+INA
V
LEA
LEA
CCO
CCO
QA
QA
CCI
Function
Logic Supply Terminal.
One of Two Complementary Outputs for Channel A. QA is logic high if the
analog voltage at the noninverting input is greater than the analog voltage at
the inverting input (provided the comparator is in the compare mode). See the
description of Pin LEA for more information.
One of Two Complementary Outputs for Channel A. QA is logic low if the analog
voltage at the noninverting input is greater than the analog voltage at the
inverting input (provided the comparator is in the compare mode). See the
description of Pin LEA for more information.
One of Two Complementary Outputs for Channel A Latch Enable. In the
compare mode (logic high), the output tracks changes at the input of the
comparator. In the latch mode (logic low), the output reflects the input state just
prior to the comparator’s being placed in the latch mode. LEA must be driven in
conjunction with LEA.
One of Two Complementary Outputs for Channel A Latch Enable. In the
compare mode (logic high), the output tracks changes at the input of the
comparator. In the latch mode (logic low), the output reflects the input state just
prior to the comparator’s being placed in the latch mode. LEA must be driven in
conjunction with LEA .
Input Supply Terminal.
Inverting Analog Input of the Differential Input Stage for Channel A. The
inverting A input must be driven in conjunction with the noninverting A input.
Noninverting Analog Input of the Differential Input Stage for Channel A. The
noninverting A input must be driven in conjunction with the inverting A input.
Programmable Hysteresis.
Programmable Hysteresis.
Noninverting Analog Input of the Differential Input Stage for Channel B. The
noninverting B input must be driven in conjunction with the inverting B input.
Inverting Analog Input of the Differential Input Stage for Channel B. The
inverting B input must be driven in conjunction with the noninverting B input.
Analog Ground.
10
1
2
3
4
5
6
7
8
9
Rev. 0 | Page 6 of 16
Pin Configuration
ADCMP552
(Not to Scale)
TOP VIEW
20
19
18
17
16
15
14
13
12
11
V
QB
QB
V
LEB
LEB
AGND
–INB
+INB
HYSB
CCO
CCO
+INA
–INA
Figure 4. ADCMP553 8-Lead MSOP
LEA
LEA
1
2
3
4
Pin Configuration
ADCMP553
(Not to Scale)
TOP VIEW
8
7
6
5
AGND
V
QA
QA
CC