sc1112a Semtech Corporation, sc1112a Datasheet - Page 15

• Manufacturer Part Number: sc1112a
• Description: Triple Low Dropout Regulator Controllers
• Manufacturer: Semtech Corporation

Theory Of Operation
The SC1112 was designed for the latest high speed mother
boards requiring a controled power up sequencing of the
Outputs, and a programable delay for the Power good sig-
nal.
Three Linear controllers have been incorperated into the
SC1112. The VTT output can be programmed to either a
1.250V or a 1.500V by applying a LOW or a HIGH control
signal to the VTTSEL pin. AGP output can also be
prgorammed via AGPSEL pin to a 1.50V or a 3.30V. The
SC1112 also provides an Adjustable output which utilizes
a resistive voltage divider.
The +5VSTBY supply will power the internal Reference,
Charge Pump, Oscillator, and the Fet controllers. After the
+5VSTBy has been established, LDO outputs will track the
VTTIN (3.30V) supply as it is applied.
An external capaitor connected to the Delay pin will pro-
gram the VTT short circuit delay time (SC
delay time (PG
During power up, an internal short circuit glitch timer will
start once the VTT Input Voltage exceeds the VTTIN
During the glitch timer immunity time, determined by the
Delay capacitor (Delay time is approximately equal to
(Cdelay*SCTH)/ISC), the short circuit protection is disabled
to allow VTT output to rise above the trip threashold (0.7V).
If the VTT output has not risen above the trip threashold
after the immunity time has elapsed, the VTT output is
latched off and will only be enabled again if either the VTT
input voltage or the 5VSTBY is cycled.
PWRGD pin is kept low during the power up, until the VTT
output has reached its PG
the PWRGD source current I
start charging the external PWRGD delay capacitor
connected to the DELAY pin. Once the capacitor is charged
above the PG
ground. A detailed timing diagram is shown on pages 4 to
5.
Applications Infomation
© 2001 Semtech Corp.
POWER MANAGEMENT
Delay_TH
td
).
(1.5V), the PWRGD pin is released from
td1.25
PG
or PG
(20uA) is enabled and will
td1.5
td
level. At that time
), and the PWRGD
TH
(1.5V).
15
Also included is an overcurrent protection circuit that moni-
tors the VTT voltage. If the output voltage drops below
700mV, as would occur during an overcurrent or short
condition, the device will pull the drive pin low and latch
off the output.
Fixed Output Voltage Options (VTT, AGP)
Please refer to the Application Circuit on Page 1. The VTT
and the AGP fixed output voltage can be programed from
a Control logic signal. Table below shows the possible Volt-
ages:
Once the VTTSEL or the AGPSEL signal is established, an
internal resistive divider is used to compare the bandgap
reference voltage with the feed back output voltage. The
drive
maintain the output voltage set by the internal resistor
divider. Referring to the block diagram on page 7.
It is possible to adjust the output voltage of the VTT or
AGP, by applying an external resistor divider to the sense
pin (please refer to Figure 1 on Page 11). Since the sense
pin
values should be selected to allow 10mA to flow through
the divider. This will ensure that variations in this current
do not adversely affect output voltage regulation. Thus a
target value for R2 (maximum) can be calculated:
The output voltage can only be adjusted upwards from the
fixed output voltage, and can be calculated using the
following equation:
R
V
2
OUT
≤
(
ADJUSTED
V
sinks
OUT
10
pin
mA
(
FIXED
)
V
=
T
)
T
a
V
0
0
1
1
S
voltage
OUT
E
Ω
L
nominal
(
FIXED
A
G
P
)
0
1
0
1
S
•
E
⎛
⎜
⎝
L
1
is
+
R
R
. 1
. 1
. 1
. 1
V
100μA,
1
2
5 2
5 2
0 5
0 5
T
⎞
⎟
⎠
then
T
V
V
V
V
+
R
1
•
. 1
. 3
. 1
. 3
100
A
0 5
0 3
0 5
0 3
G
adjusted
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the
P
SC1112
V
V
V
V
μ
A
Volts
resistor
to