clc431 National Semiconductor Corporation, clc431 Datasheet - Page 5

• Manufacturer Part Number: clc431
• Description: Dual Wideband Monolithic Op Amp With Disable
• Manufacturer: National Semiconductor Corporation

front page). Also note that both amplifiers are guaranteed
to be enabled if all three of these pins are unconnected.
Fig. 1 illustrates the single-ended mode of the CLC431's
disable feature for logic families such as TTL and CMOS.
In order to operate properly, V
thereby biasing DIS to approximately +1.4V through the
two internal series diodes. For single-ended operation,
DIS should be left floating. Applying a TTL or CMOS logic
"high" (i.e. >2.0Volts) to DIS will switch the tail current of
the differential pair to Q1 and "shut down" Q2 which
results in the disabling of that channel of the CLC431.
Alternatively, applying a logic "low" (i.e. <0.8Volts) to DIS
will switch the tail current from Q1 to Q2 effectively
enabling that channel. If DIS is left floating under single-
ended operation, then the associated amplifier is guaran-
teed to be disabled .
The disable feature of the CLC431 is such that DIS and
DIS have common-mode input voltage ranges of (+V
to (-V
temperature range. Internal clamps (not shown) protect
the DIS input from excessive input voltages that could
otherwise cause damage to the device. This condition
occurs when enough source current flows into the node
so as to allow DIS to rise to V
once DIS exceeds DIS by 1.5Volts and guarantees that
V
DIS
CMOS
(ground referenced) does not exceed 4.7Volts.
TTL
CC
ECL
V
V
+3V) and are so guaranteed over the commercial
non-inv
non-inv
V
V
inv
inv
DIS
DIS
-5V
-5V
510
510
½CLC431
+V
+V
½CLC431
CC
CC
100k
100k
Fig. 1
Fig. 2
+V
Q
+V
Q
1
CC
1
CC
CC
+
-
RTTL
. This clamp is activated
+
-
Q
2
Q
100k
must be grounded,
2
100k
+V
CC
+V
CC
DIS
V
V
RTTL
out
DIS
V
V
RTTL
CC
out
)
5
Fig. 2 illustrates the differential mode of the CLC431's
disable feature for ECL-type logic. In order for this mode
to operate properly, V
and DIS are to be connected directly to the ECL gate as
illustrated. Applying a differential logic "high" ( DIS - DIS
from Q2 to Q1 and results in the disabling of that CLC431
channel. Alternatively, applying a differential logic "low"
( DIS - DIS
differential pair from Q1 to Q2 and results in the enabling
of that same channel. The internal clamp, mentioned
above, also protects against excessive differential volt-
ages up to 30Volts while limiting input currents to <3mA.
DC Performance
A current-feedback amplifier’s input stage does not have
equal nor correlated bias currents, therefore they cannot
be cancelled and each contributes to the total DC offset
voltage at the output by the following equation:
The input resistor R
from the non-inverting input back towards the source. For
inverting DC-offset calculations, the source resistance
seen by the input resistor R
output offset calculation as a part of the non-inverting
gain equation. Application note OA-7 gives several circuits
for DC offset correction.
Layout Considerations
It is recommended that the decoupling capacitors (0.1 F
ceramic and 6.8 F electrolytic) should be placed as close
as possible to the power supply pins to insure a proper
high-frequency low impedance bypass. Careful attention
to circuit board layout is also necessary for best
performance. Of particular importance is the control of
parasitic capacitances (to ground) at the output and
invering input pins. See CLC431/432 Evaluation Board
literature for more information.
Applications Circuits
2:1 Video Mux (CLC431)
Fig. 3 illustrates the connections necessary to configure
the CLC431 as a 2:1 multiplexer in a 75 system. Each
of the two CLC431's amplifiers is configured with a non-
inverting gain of +2V/V using 634
gain-setting (R
lower than that recommended in order to compensate for
the reduction of loop-gain that results from the inclusion
of the 50
resistor serves to isolate the output of the active channel
from the impedance of the inactive channel yet does not
affect the low output impedance of the active channel.
Notice that for proper operation V
and V
with the disable feature are to be connected as follows:
DIS1 and DIS2 (pins 3 & 10) are connected together as
well as DIS2 and DIS1 (pins 5 & 12). Channel 1 is
selected with the application of a logic "low" to SELECT
while a logic "high" selects Channel 2.
0.4Volts) switches the tail current of the differential pair
V
offset
RTTL
2 (pin 9) is unconnected. The pins associated
resistor (R
I
bn
-0.4Volts) switches the tail current of the
g
) resistors. The feedback resistor value is
R
s
s
is that resistance seen when looking
1
RTTL
i
) in the feedback loop. This 50
R
R
must be left floating while DIS
g
f
g
must be included in the
V
RTTL
io
1 (pin 13) is grounded
1
feedback (R
R
http://www.national.com
R
g
f
I
bi
R
f
f
) and