clc440 National Semiconductor Corporation, clc440 Datasheet - Page 5

• Manufacturer Part Number: clc440
• Description: High-speed, Low-power, Voltage Feedback Op Amp
• Manufacturer: National Semiconductor Corporation

Figure 1 shows the noise model for the non-inverting
amplifier configuration. The model includes all of the
following noise sources:
The total equivalent input noise density is calculated
by using the noise model shown. Equations 1 and 2
represent the noise equation and the resulting equation
for noise figure.
Equation 1: Noise Equation
Equation 2: Noise Figure Equation
The noise figure is related to the equivalent source
resistance (R
R
recommended:
R
minimum and is approximated by:
Figure 2 is a plot of NF vs R
The NF curves for both Unterminated and Terminated
systems are shown. The Terminated curve assumes R
= R
tances including R
Layout Considerations
A proper printed circuit layout is essential for achieving
high
evaluation boards for the CLC440 (CLC730055-DIP,
CLC730060-SOIC) and suggests their use as a guide for
high frequency layout and as an aid in device testing and
characterization.
e
NF 10LOG
g.
OPT
ni
Figure 1: Non-inverting Amplifier Noise Model
T
•
•
•
•
•
To minimize noise figure, the following steps are
. The table indicates the NF for various source resis-
Input voltage noise (e
Input current noise (i
Thermal Voltage Noise (e
external resistor
Minimize R
Choose the optimum R
is the point at which the NF curve reaches a
frequency
e
n
4kTR seq
2
R
i
e
R
n
seq
n
seq
2
R
seq
2
seq
*
R
) and the parallel combination of R
= R
i
f
n
seq
= R
IIR
2
s
s
s
II R
R
= R
performance.
2
g
for Unterminated Systems
seq
*
*
T
R
i
n+
i
OPT
for Terminated Systems
R IIR
2
n-
e
OPT
*
n
f
n
*
R IIR
s
.
n
R
= i
CLC440
f
+
)
-
g
with R
g
s
4kTR g
4kTR
2
(R
n+
e
g
i
t
n
) associated with each
n
2
OPT
= i
R
seq
4kTR
f
f
= 0, R
n-
4kTR
National
)
)
4kTR f
seq
*
seq
g
=
4kT R IIR
4kT R IIR
(A
provides
v
f
f
= +1).
f
g
and
g
s
5
These boards were laid out for optimum, high-speed
performance. The ground plane was removed near the
input and output pins to reduce parasitic capacitance.
And all trace lengths were minimized to reduce series
inductances.
Supply bypassing is required for the amplifiers
performance.
impedance return current path at the supply pins. They
also provide high frequency filtering on the power supply
traces. 6.8 F tantalum, 0.01 F ceramic, and 500pF
ceramic capacitors are recommended on both supplies.
Place the 6.8 F capacitors within 0.75 inches of the
power pins, and the 0.01 F and 500pF capacitors less
than 0.1 inches from the power pins.
Dip sockets add parasitic capacitance and inductance
which can cause peaking in the frequency response and
overshoot in the time domain response. If sockets are
necessary, flush-mount socket pins are recommended.
The device holes in the 730055 evaluation board are
sized for Cambion P/N 450-2598 socket pins, or their
functional equivalent.
Transimpedance Amplifier
The low 2.5pA/ Hz input current noise and unity gain
stability make the CLC440 an excellent choice for
transimpedance applications.
low noise transimpedance amplifier that is commonly
implemented with photo diodes. R
ance gain. The photo diode current multiplied by R
determines the output voltage.
Figure 3: Transimpedance Amplifier Configuration
Figure 2: Noise Figure vs. Source Resistance
25
20
15
10
I
Representation
5
0
in
Photo Diode
Noise Figure vs. Source Resistance
10
Applications Circuits
Unterminated
The bypass capacitors provide a low
C
d
100
Source Resistance ( )
Terminated
R
R
s
50
OPT
( )
R
opt
NF Unterminated
= 1400
1k
CLC440
12.03dB
+
3.13dB
-
R
opt
R
= 2800
C
Figure 3 illustrates a
f
f
f
V
sets the transimped-
out
NF Terminated
10k
17.90dB
6.15dB
= -I
http://www.national.com
in
* R
100k
f
V
out
f