clc410 National Semiconductor Corporation, clc410 Datasheet - Page 10

• Manufacturer Part Number: clc410
• Description: Fast Settling, Video Op Amp With Disable
• Manufacturer: National Semiconductor Corporation

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Application Division
and band width, while decreasing it will increase the loop
gain possibly leading to inadequate phase margin and
closed-loop peaking. Conversely, fixing R
quency response constant while the closed-loop gain can be
adjusted using R
The CLC410 departs from this idealized analysis to the
extent that the inverting input impedance is finite. With the
low quiescent power of the CLC410, Z
in loop gain and bandwidth at high gain settlings, as given by
equation 2. The second term in Equation 2 accounts for the
division in feedback current that occurs between Z
R
bandwidth can be circumvented as described in “Increasing
Bandwidth at High Gains.” Also see “Current Feedback Am-
plifiers” in the National Databook for a thorough discussion
of current feedback op amps.
Increasing Bandwidth At High Gains
Bandwidth may be increased at high closed-loop gains by
adjusting R
that occur at these high gain settlings due to current division
at the inverting input. An approximate relationship may be
obtained by holding the LG expression constant as the gain
is changed from the design point used in the specifications
(that is, R
gives,
where A
get the specified R
value gives stable performance with improved bandwidth.
DC Accuracy and Noise
Since the two inputs for the CLC410 are quite dissimilar, the
noise and offset error performance differs somewhat from
that of a standard differential input amplifier. Specifically, the
inverting input current noise is much larger than the
non-inverting current noise. Also the two input bias currents
are physically unrelated rendering bias current cancellation
through matching of the inverting and non-inverting pin re-
sistors ineffective.
f
iR
g
at the inverting node of the CLC410. This decrease in
V
is the non-inverting gain. Note that with A
f
f
= 250
and R
g
.
g
f
and R
= 250 , while at higher gains, a lower
to make up for the losses in loop gain
g
= 250 ). For the CLC400 this
(Continued)
i
)50 leading to drop
f
will hold the fre-
V
= +2 we
i
and
(3)
10
In Equation 4, the output offset is the algebraic sum of the
equivalent input voltage and current sources that influence
DC operation. Output noise is determined similarly except
that a root-sum-of-squares replaces the algebraic sum. R
the non-inverting pin resistance.
An important observation is that for fixed R
referred to the input improve as the gain is increased (divide
all terms by 1+R
where noise figure improves as a gain increases.
The input noise plot shown in the CLC400 datasheet applies
equally as well to the CLC410.
Capacitive Feedback
Capacitive feedback should not be used with the CLC410
because of the potential for loop instability. See Application
Note OA-7 for active filter realizations with the CLC410.
Offset Adjustment Pin
Pin 1 can be connected to a potentiometer as shown in
Figure 1 and used to adjust the input offset of the CLC410.
Full range adjustment of
input offset adjustment range. Pin 1 should always be by-
passed to ground with a ceramic capacitor located close to
the package for best settling performance.
Printed Circuit Layout
As with any high frequency device, a good PCB layout will
enhance performance. Ground plane construction and good
power supply bypassing close to the package are critical to
achieving full performance. In the non-inverting configura-
tion, the amplifier is sensitive to stray capacitance to ground
at the inverting input. Hence, the inverting node connections
should be small with minimal coupling to the ground plane.
Shunt capacitance across the feedback resistor should not
be used to compensate for this effect.
Parasitic or load capacitance directly on the output will intro-
duce additional phase shift in the loop degrading the loop
phase margin and leading to frequency response peaking. A
small series resistor before the capacitance effectively de-
couples this effect. The graphs on the preceding page illus-
trates the required resistor value and resulting performance
vs. capacitance.
Precision buffed resistors (PRP8351 series from Precision
Resistive Products) with low parasitic reactances were used
to develop the data sheet specifications. Precision carbon
composition resistors will also yield excellent results. Stan-
dard spirally-trimmed RN55D metal film resistors will work
with a slight decrease in bandwidth due to their reactive
nature at high frequencies.
Evaluation PC boards (part no. 730013 for through-hole and
730027 for SOIC) for the CLC404 are available.
Equation 4
Output Offset V
VIO (1+R
f
/R
g
)
±
f
/R
O
IBIx R
=
g
). A similar result is obtained for noise
±
IBNx R
f
±
5V on pin 1 will yield a
S
(1+R
f
/R
g
)
±
f
, offsets as
±
10mV
s
is