clc412 National Semiconductor Corporation, clc412 Datasheet - Page 7

• Manufacturer Part Number: clc412
• Description: Dual Wideband Video Op Amp
• Manufacturer: National Semiconductor Corporation

controlled as shown in Typical Performance plot labeled
“Small-Signal Channel Matching”. The measurements
were performed with SMT components using the
recommended value of feedback resistor of 634
gain of +2V/V. The pulse response plot labeled "Pulse
Matching" found below shows the group delay matching
between amplifiers of the CLC412. The circuit topology
is described in Figure 3.
The CLC412's amplifiers, built on the same die, provide
the advantage of having tightly matched DC
characteristics. The typical DC matching specifications
of the CLC412 are:
Slew Rate and Settling Time
One of the advantages of current-feedback topology is
an inherently high slew rate which produces a wider full-
power bandwidth. The CLC412 has a typical slew rate of
1300V/ s. The required slew rate for a design can be
calculated by the following equation: SR=2 fV
Careful attention to parasitic capacitances is critical to
achieving the best settling time performance. The CLC412
has a typical short term settling time to 0.05% of 12ns
for a 2 volt step. Also, the amplifier is virtually free of any
long term thermal tail effects at low gains as shown in
the Typical Performance plot labeled “Long Term
Settling Time”.
When measuring settling time, a solid ground plane
should be used in order to reduce ground inductance
which can cause common-ground-impedance coupling.
Power supply and ground trace parasitic capacitances
and the load capacitance will also affect settling time.
Placing a series resistor (R
recommended for optimal settling time performance when
driving a capacitive load. The Typical Performance plot
labeled “R
provides a means for selecting a value of R
capacitive load. The plot also shows the resulting settling
time to 0.05 and 0.01%.
DC & Noise Performance
A current-feedback amplifier’s input stage does not have
equal nor correlated bias currents, therefore they cannot
be canceled and each contributes to the total DC offset
Vio = ±0.60mV, Ibn = ±0.25 A, Ibi = ±1.5 A.
s
and Settling Time vs. Capacitive Load”
s
) at the output pin is
s
for a given
pk
at a
7
voltage at the output by the following equation:
The input resistor R
non-inverting input back towards the source. For inverting
DC-offset calculations, the source resistance seen by
the input resistor R
calculation as a part of the non-inverting gain equation.
Application note OA-7 gives several circuits for DC offset
correction. The noise currents for the inverting and non-
inverting inputs are graphed in the Typical Performance
plot labeled “Equivalent Input Noise”. A more complete
discussion of amplifier input-referred noise and external
resistor noise contribution can be found in OA-12.
Differential Gain & Phase
The CLC412 can drive multiple video loads with very low
differential gain and phase errors. The Typical
Performance plots labeled “Differential Gain vs.
Frequency” and "Differential Phase vs. Frequency" show
performance for loads from 1 to 4. The Electrical
Characteristics table also specifies guaranteed
performance for one 150 load at 4.43MHz. For NTSC
video, the guaranteed performance specifications also
apply. Application note OA-08, “Differential Gain and
Phase for Composite Video Systems,” describes in detail
the techniques used to measure differential gain and
phase.
I/O Voltage & Output Current
The usable common-mode input voltage range (CMIR)
of the CLC412 specified in the Electrical Characteristics
table of the data sheet shows a range of ±2.2 volts.
Exceeding this range will cause the input stage to saturate
and clip the output signal.
The output voltage range is determined by the load
resistor and the choice of power supplies. With ±5 volts
the class A/B output driver will typically drive +3.1/-2.7
volts into a load resistance of 100 . Increasing the
supply voltages will change the common-mode input and
output voltage swings while at the same time increase
the internal junction temperature. The output voltage for
different load resistors can be determined from the data
sheet plots labeled “Frequency Response vs. Load (R
and “Maximum Output Swing vs. Frequency".
Applications Circuits
Single-to-Differential Line Driver.
The CLC412's well matched AC channel-response allows
a single-ended input to be transformed to highly-matched
push-pull driver. From a 1V single-ended input the circuit
of Figure 4 produces 1V differential signal between the
two outputs. For larger signals, the input voltage divider
(R
2. To achieve the same performance when driving a
matched load, see Figure 3.
1
=2R
V
offset
2
) is necessary to limit the input voltage on channel
I
bn
R
g
must be included in the output offset
in
s
is the resistance looking from the
1
R
R
g
f
V
io
1
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R
g
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bi
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