clc426 National Semiconductor Corporation, clc426 Datasheet - Page 5

• Manufacturer Part Number: clc426
• Description: Wideband, Low-noise, Voltage Feedback Op Amp
• Manufacturer: National Semiconductor Corporation

Supply Current Adjustment
The CLC426's supply current can be externally adjusted
downward from its nominal value to less than 2mA by
adding an optional resistor (R
negative supply as shown in fig 2. The plot labeled "Open-
Loop Gain vs. Supply Current" illustrates the influence
that supply current has over the CLC426's open-loop
response. From the plot it is seen that the CLC426 can be
compensated for unity-gain stability by simply lowering
its supply current. Therefore lowering the CLC426's sup-
ply current effectively reduces its open-loop gain to the
point that there is adequate phase margin at unity gain
crossover. The plot labeled "Supply Current vs. R
provides the means for selecting the value of R
produces the desired supply current. The curve in the plot
represents nominal processing but a ±12% deviation over
process can be expected. The two plots labeled "Voltage
Noise vs. Supply Current" and "Current Noise vs. Supply
Current" illustrate the CLC426 supply current's effect over
its input-referred noise characteristics.
Driving Capacitive Loads
The CLC426 is designed to drive capacitive loads with the
addition of a small series resistor placed between the
output and the load as seen in fig. 3. Two plots located in
the Typical Performance section illustrate this technique
for both frequency domain and time domain applications.
The plot labeled "Frequency Response vs. Capacitive
Load" shows the CLC426's resulting AC response to
various capacitive loads. The values of R
were chosen to maximize the CLC426's AC response
(limited to 1dB peaking).
The second plot labeled "Settling Time vs. Capacitive
Load" provides the means for the selection of the value of
R
from the plot, for a given capacitive load R
the curve labeled "R
0.05% can then be estimated from the curve labeled "T
to 0.05%". The plot of fig. 4 shows the CLC426's pulse
response for various capacitive loads where R
chosen from the plot labeled "Settling Time vs. Capaci-
s
which minimizes the CLC426's settling time. As seen
s
". The resulting settling time to
Fig. 2
Fig. 3
p
) between pin 8 and the
s
is chosen from
s
in this plot
s
has been
p
that
p
s
"
5
tive Load".
Faster Settling
The circuit of fig. 5 shows an alternative method for driving
capacitive loads that results in quicker settling times. The
small series-resistor, R
open-loop output resistance, R
tance. The small feedback-capacitance, C
provide a high-frequency bypass between the output and
inverting input. The phase lead introduced by C
sates for the phase lag due to C
stability. The following equations provide values of R
C
gain.
the result of the two methods of capacitive load driving
mentioned above while driving a 100pF||1k load.
f
for a given load capacitance and closed-loop amplifier
R
C
s
1
R
1
out
R
R
R
R
g
f
g
f
s
, is used to decouple the CLC426's
;
2
C
where R
Fig. 4
Fig. 5
Fig. 6
L
R
R
out
out
L
g
and therefore restores
out
, from the load capaci-
6
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f
, is used to
The plot in
fig. 6 shows
f
compen-
Eq. 1
Eq. 2
s
and