clc409 National Semiconductor Corporation, clc409 Datasheet - Page 8

• Manufacturer Part Number: clc409
• Description: Very Wideband, Low Distortion Monolithic Op Amp
• Manufacturer: National Semiconductor Corporation

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Application Division
CLC409 does not show an intercept type performance.
(where the relative spurious levels change at a 2X rate vs.
the test tone powers), due to an internal full power bandwidth
enhancement circuit that boosts the performance as the
output swing increases while dissipating negligible quiescent
power under low output power conditions. This feature en-
hances the distortion performance and full power bandwidth
to match that of much higher quiescent supply current parts.
Figure 3 shows a typical application using the CLC409 to
drive an ADC. The series resistor, R
output and the ADC input is critical to achieving best system
performance. This load capacitance, if applied directly to the
output pin, can quickly lead to unacceptable levels of ringing
in the pulse response. The plot of R
on the previous page is an excellent starting point for setting
R
time into a fixed discrete capacitive load. Several additional
constraints should be considered, however, in driving the
capacitive input or an ADC.
There is an option to increase R
input for either noise or Nyquist bandlimiting purposes. In-
creasing R
large input glitch due to switching transients coupling
s
. The value derived in that plot minimizes the step settling
s
FIGURE 3. Input Amplifier to ADC
too much, however, can induce an unacceptably
s
, bandlimiting at the ADC
s
s
(Continued)
and settling time vs. C
, between the amplifier
01274820
L
8
through from the convert signal. Also, C
voltage dependent capacitance. This input impedance
non-linearity will induce distortion terms that will increase as
R
recommended R
optimizing system performance.
DC Accuracy and Noise
The CLC409 offers an improved offset voltage over the pin
compatible CLC400 low gain amplifier. The offset adjustment
available on the CLC400 was therefore not included in this
part. The Output Offset equation below shows the output
offset computation equation for the non-inverting configura-
tion with an example using the typical bias current and offset
specifications for A
This low output offset voltage is a marked improvement over
earlier very high speed amplifiers. Further improvement in
the output offset voltage and drift is possible using the com-
posite amplifiers described in Application Note OA-7.
The two input bias currents are physically unrelated in both
magnitude and polarity for the current feedback topology. It
is not possible, therefore, to cancel their effects by matching
the source impedance for the two inputs (as is commonly
done for matched input bias current devices).
The total output noise is computed in a similar fashion to
output offset voltage. Using the input noise voltage and two
input noise currents, the output noise is developed through
the same gain equations for each term but combined as the
square root of the sum of squared contributing elements.
See Application Note OA-12 for a full discussion of noise
calculations for current feedback amplifiers.
Printed Circuit Layout
As with any high speed component, a careful attention to the
board layout is necessary for optimum performance. Evalu-
ation PC boards (CLC730013-DIP, CLC730027-SOIC, and
CLC730068-SOT) for the CLC409 are available. This addi-
tional supply bypassing capacitor, C
to the board if desired. Further layout suggestions can be
found in Application Note OA-15.
s
Output Offset
V
Example Computation for A
V
is increased. Only slight adjustments up or down from the
O
O
=(
=(
±
±
I
10µA (25Ω)
bn
R
in
±
V
s
io
value should therefore be attempted in
V
)(1+R
±
= +2.
0.5mV)2
f
/R
g
)
±
V
±
I
=+2, R
bi
10µA (250Ω)=
R
f
ss
, can easily be added
f
=250Ω, R
in
is oftentimes a
±
3.25mV
in
=25Ω: