add8616a8a-75b ETC-unknow, add8616a8a-75b Datasheet - Page 3

• Manufacturer Part Number: add8616a8a-75b
• Description: Double Data Rate Sdram
• Manufacturer: ETC-unknow

Pin Description
Block Diagram
Rev 2 April, 2002
DQ0~DQ15 Data
V
BS0~BS1
VDD/VSS
CK, /CK
A0~A12
DDQ
A-Data
VREF
/RAS
/CAS
CKE
/WE
PIN
/CS
NC
/V
SSQ
CKE
CK
Address
/CAS
/RAS
/WE
/CS
Address
Banks Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Output Power/Ground
Reference Voltage
System Clock
Clock Enable
Chip Select
Power Supply/Ground
No Connection
Clock
Generator
NAME
Mode
Register
Differential clock input.
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
Disables or Enables device operation by masking or enabling all input
except CK, CKE and DQ
Row / Column address are multiplexed on the same pins.
Row address : A0~A12
Column address : A0~A9
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Data inputs / outputs are multiplexed on the same pins.
Latches row addresses on the positive edge of the CLK with /RAS low
Latches Column addresses on the positive edge of the CLK with /CAS
low
Enables write operation and row recharge.
Power and Ground for the input buffers and the core logic.
Power supply for output buffers.
Reference voltage for inputs for SSTL interface.
This pin is recommended to be left No Connection on the device.
Column
Address
Refresh
Counter
3
Address
Refresh
Counter
Buffer
Buffer
&
&
FUNCTION
Data Control Circuit
Column Decoder
Amplifier
Bank0
Bank3
Bank2
Bank1
ADD8616A8A
DQ0~DQn
DQM
DQS