lt5518 Linear Technology Corporation, lt5518 Datasheet - Page 12

• Manufacturer Part Number: lt5518
• Description: 1.5ghz?2.4ghz High Linearity Direct Quadrature Modulator
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
LT5518
coupling capacitor can be inserted in the RF output line.
This is strongly recommended during a 1dB compression
measurement.
Enable Interface
Figure 7 shows a simplifi ed schematic of the EN pin inter-
face. The voltage necessary to turn on the LT5518 is 1.0V.
To disable (shutdown) the chip, the Enable voltage must
be below 0.5V. If the EN pin is not connected, the chip is
disabled. This EN = Low condition is guaranteed by the
75kΩ on-chip pull-down resistor. It is important that the
voltage at the EN pin does not exceed V
0.5V. If this should occur, the full chip supply current could
be sourced through the EN pin ESD protection diodes.
Damage to the chip may result.
Evaluation and Demo Boards
Figure 8 shows the schematic of the evaluation board that
was used for the measurements summarized in the Elec-
trical Characteristics tables and the Typical Performance
Characteristic plots.
Figure 9 shows the demo board schematic. Resistors R3,
R4, R10 and R11 may be replaced by shorting wires if a
fl at frequency response to DC is required. A good ground
connection is required for the exposed pad of the LT5518
package. If this is not done properly, the RF performance
will degrade. The exposed pad also provides heat sink-
ing for the part and minimizes the possibility of the chip
overheating. R7 (optional) limits the Enable pin current in
the event that the Enable pin is pulled high while the V
inputs are low. In Figures 10, 11 and 12 the silk screen
and the demo board PCB layouts are shown. If improved
LO and Image suppression is required, an LO feedthrough
calibration and an Image suppression calibration can be
performed.
12
EN
Figure 7. EN Pin Interface
U
V
CC
U
75k
25k
W
5518 F07
CC
by more than
U
CC
BBQM
BBIM
Figure 10. Component Side Silk Screen of Demo Board
V
BOARD NUMBER: DC831A
V
J1
J5
CC
CC
BBQM
BBIM
Figure 8. Evaluation Board Circuit Schematic
EN
EN
Figure 9. Demo Board Circuit Schematic
LO
IN
E1
LO
IN
J1
J5
R5
52.3Ω
R12
52.3Ω
E4
J4
J4
GND
100
100
R1
R7
3.3nF
3.3nF
C1
C5
1
2
3
4
3.01k
3.01k
1
2
3
4
R10
E3
R3
GND
GND
EN
GND
LO
GND
EN
GND
LO
GND
16
BBMQ GND
16
BBMI
5
BBMQ GND
BBMI
5
BOARD NUMBER: DC729A
15
15
6
5.62k
GND
5.62k
6
GND
R8
LT5518
R1
LT5518
14
14
BBPQ V
7
BBPI V
BBPQ V
7
BBPI V
13
3.3nF
3.3nF
13
8
C2
C6
8
CC
CC
3.01k
3.01k
CC
CC
GND
GND
GND
GND
R11
R4
GND
GND
GND
GND
RF
RF
C1
100nF
C4
100nF
5.62k
12
11
10
9
17
R2
12
11
10
9
17
J2
J6
BBIP
BBQP
5.62k
5518 F08
R6
52.3Ω
R13
52.3Ω
C2
100nF
J3
J3
R9
C3
100nF
RF
OUT
RF
OUT
V
V
CC
J2
J6
CC
E2
BBIP
BBQP
5518 F09
5518f