adl5386 Analog Devices, Inc., adl5386 Datasheet - Page 22

• Manufacturer Part Number: adl5386
• Description: 50 Mhz To 2200 Mhz Quadrature Modulator With Integrated Detector And Vva
• Manufacturer: Analog Devices, Inc.

ADL5386
POWER SUPPLY AND GROUNDING
The VPOS supply pins should be connected to a common 5 V
supply. This supply can vary from 4.75 to 5.5 V. The power
supply pins should be adequately decoupled using 0.1 μF
capacitors located close to each pin. Adjacent pins can share
decoupling capacitors, as shown in Figure 41.
The COMM ground pins should be connected to a common
low impedance ground plane. The exposed paddle on the
underside of the package is also soldered to a low thermal
and electrical impedance ground plane. If the ground plane
spans multiple layers on the circuit board, the layers should be
stitched together with nine vias under the exposed paddle. The
Analog Devices, AN-772 Application Note, A Design and
Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP), discusses the thermal and electrical grounding of the
LFCSP in detail.
DEVICE ENABLE AND DISABLE
The IQ modulator section can be enabled or disabled by pulling
the ENBL pin high or low, respectively. The detector section of
the circuit can be disabled by pulling the TADJ pin high.
BASEBAND INPUTS
The baseband inputs, QBBP, QBBN, IBBP, and IBBN, must be
driven from a differential source. The nominal drive level of
1.4 V p-p differential (700 mV p-p on each pin) is biased to a
common-mode level of 500 mV dc. This drive level generates
an output power level (at MODOUT) of between 2 dBm and
6 dBm based on output frequency.
The dc common-mode bias level for the baseband inputs can
range from 400 mV to 600 mV. This results in a reduction in the
usable input ac swing range. The nominal dc bias of 500 mV allows
for the largest ac swing, limited on the bottom end by the ADL5386
input range and on the top end by the output compliance range
on most Analog Devices DACs.
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LO INPUT
A single-ended LO signal is applied to the LOIP pin through an
ac coupling capacitor. A square wave or a sine wave can be used
to drive the LO port. The recommended LO drive power is
−7 dBm. An LO power level of −7 dBm is the minimum level
that should be used for output frequencies below 140 MHz
(f
LO power can be reduced to −13 dBm. The LO return pin, LOIN,
should be ac-coupled to ground though a low impedance path.
The nominal LO drive of −7 dBm can be increased to up to
+2 dBm. The effect of LO power on sideband suppression and
carrier feedthrough is shown in Figure 15 and Figure 16.
AGC MODE
The on-board log amp power detector of the ADL5386 can be
used to implement an automatic output power control (commonly
referred to as AGC) loop that effectively linearizes the transfer
function of the VVA. To implement this mode, a number of
circuit modifications are necessary.
A portion of the output signal of the VVA is coupled back to the
input of the log amp detector. This can be done with a power
splitter or with a directional coupler as shown in Figure 42.
The coupling factor or power split ratio should be set so that
the detector never sees a power level that is greater than about
−10 dBm (the transfer function of the detector loses some linearity
above this level). In the example shown in Figure 42, a maximum
output power from the VVA/modulator of +3 dBm is desired. A
directional coupler with a coupling factor of approximately +15 dB
drops this level down to −12 dBm at the input of the detector.
The input signal to the detector produces a current that is
drawn from the summing node (Pin CLPF) into the detector
block. A setpoint voltage that is applied to the VSET pin is
converted into a current that is pumped into the summing
node. If these two currents are not equal, the net current flows
into or out of the CLPF capacitor on Pin 4. This changes the
voltage on the CLPF node that in turn changes the voltage on
the VDET/VCTL pin. This pin is internally connected to the
attenuation control pin of the VVA. Therefore, the attenuation
control voltage on Pin 7 (VDET/VCTL) increases or decreases
until the I
reached, the voltage on CLPF (and thereby on the control
voltage node of the VVA) is held steady.
LO
≤ 280 MHz). At output frequencies above 140 MHz, the
SET
and I
DET
currents match. When this equilibrium is